Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital worst-case timing analysis October 2019 659 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. the timing ambiguity result that represents a primitive's output change. For example, consider the model of a BUF device in the following figure. U5 BUF $G_DPWR $G_DGND IN1 OUT1 ; BUFFER model + T_BUF IO_STD .MODEL T_BUF UGATE ( ; BUF timing model + TPLHMN=15ns TPLHTY=25ns TPLHMX=40ns + TPHLMN=12ns TPHLTY=20ns TPHLMX=35ns) Figure 16-1 Timing ambiguity example one. The application of the instantaneous 0-1 transition at 5nsec in this example produces a corresponding output result. Given the delay specifications in the timing model, the output edge occurs at a MIN of 15nsec later and a MAX of 40nsec later. The region of ambiguity for the output response is from 20 to 45nsec (from TPLHMN and TPLHMX values). Similar calculations apply to a 1-0 transition at the input, using TPHLMN and TPHLMX values. 20 5 45