Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide October 2019 655 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. 16 Digital worst-case timing analysis This chapter deals with worst-case timing analysis and includes the following sections: ■ Digital worst-case timing on page 655 ■ Starting digital worst-case timing analysis on page 658 ■ Simulator representation of timing ambiguity on page 658 ■ Propagation of timing ambiguity on page 660 ■ Identification of timing hazards on page 661 ■ Convergence hazard on page 661 ■ Critical hazard on page 662 ■ Cumulative ambiguity hazard on page 663 ■ Reconvergence hazard on page 665 ■ Glitch suppression due to inertial delay on page 667 ■ Methodology on page 668 Note: This entire chapter describes features that are not included in PSpice. Digital worst-case timing Manufacturers of electronic components generally specify component parameters (such as propagation delays in the case of logic devices) as having tolerances. These are expressed as either an operating range, or as a spread around a typical operating point. The designer then has some indication of how much deviation from