Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital worst-case timing analysis October 2019 658 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Starting digital worst-case timing analysis To set up a digital worst-case timing analysis: 1. In the Simulation Settings dialog box, click the Options tab. See Setting up analyses on page 419 for a description of the Simulation Settings dialog box. 2. Select the General node in the Gate-level Simulation tree Structure of the Options tab. 3. In the Timing Mode frame, check Worst-case (min/max) 4. In the Initialize all flip-flops drop-down list, select X. 5. Set the Default I/O level for A/D interfaces to 1. 6. Click OK. 7. Start the simulation as described in Starting a simulation on page 436. Simulator representation of timing ambiguity PSpice A/D uses the five-valued state representation {0,1,R,F,X}, where R and F represent rising and falling transitions, respectively. Any R or F transitions can be thought of as ambiguity regions. Although the starting and final states are known (example: R is a 0 → 1 transition), the exact time of the transition is not known, except to say that it occurs somewhere within the ambiguity region. The ambiguity region is the time interval between the earliest and the latest time that a transition could occur. Timing ambiguities propagate through digital devices via whatever paths are sensitized to the specific transitions involved. This is normal logic behavior. The delay values (MIN, TYP, or MAX) skew the propagation of such signals by whatever amount of propagation delay is associated with each primitive instance. When worst-case (MIN/MAX) timing operation is selected, both the MIN and the MAX delay values are used to compute the duration of