Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Creating and editing models October 2019 266 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Junction FET Test Node Mapping Node Port name TERM_ID Depletion current terminal TERM_IG Gate current terminal NODE_VD Depletion voltage node NODE_VG Gate voltage node NODE_VS Source voltage node