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PSpice User Guide Digital worst-case timing analysis October 2019 668 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. In the analysis of reconvergent fanout cases (where common ambiguity is recognized), it is possible that conflicting signal ambiguities may still overlap at the inputs to a primitive, even after factoring out the commonality. In such cases, where the amount of overlap is less than the inertial delay of the device, the prediction of a glitch is also suppressed by the simulator (see Figure 16-15). In this case, factoring out the 15nsec common ambiguity still results in a 5nsec overlap of conflicting states. The glitch is suppressed, however, because 5nsec is less than TPLHMX-TPLHMN (the computed inertial delay value of the AND gate, 6nsec). Note: Glitch suppression can be overridden by setting the pulse-width rejection threshold parameter (TPWRT) in the device's I/O Model. Methodology Note: This is not intended to be a comprehensive discussion of the application of digital worst-case timing simulation in the design process. Rather, it is a suggested starting point for understanding the results of your simulation. Combining component tolerances and the circuit design's functional response to a specific stimulus presents a challenge. You must make sure that all the finished circuits will operate properly. Well-designed systems have a high degree of immunity from the effects of varying combinations of individual component tolerances. Digital worst-case timing simulation can help identify design problems, depending upon the nature of the stimulus applied to the design. You can use the simulation of signal propagation through the 25 75 55 90 TPLHMN=40 TPLHMX=60 TPLHMN=10 TPLHMX=45 15 30 TPLHMN=4 TPLHMX=10 Figure 16-15 Glitch suppression example three.