Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Convergence and "time step too small errors" October 2019 844 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. (almost) no leakage resistance and would cause the junction's voltage to go beyond 1e10 volts. ■ Switches PSpice switches have gain in their transition region. If several are cascaded then the cumulative gain can easily exceed the derivative limit of 1e14. This can happen when modeling simple logic gates using totem-pole switches and there are several gates cascaded in series. Usually a cascade of two switches works but three or more can cause trouble. PSpice Options ■ Increase ITL1 to 400 in the .OPTIONS statement. Example: .OPTIONS ITL1=400 This increases the number of DC iterations that PSpice will perform before it gives up. In all but the most complex circuits, further increases in ITL1 won't typically aid convergence. ■ Add .NODESETs Example: .NODESET V(6)=0 Use NODESETs to set node voltages to the nearest reasonable guess at their DC values, particularly at nodes that are isolated by high impedances, and at nodes that are inputs to high gain devices. NODESETs do not "fix" the voltages at these nodes. They hold these voltages at the specified value while the rest of the circuit converges to a reasonably stable point, and then "releases" these voltages for a few more iterations to find the final, complete solution. Removing these voltages from the initial iterations, when voltages and currents are varying widely helps PSpice achieve convergence. ■ STEPGMIN Specifying the circuit analysis option STEPGMIN enables this (either using .OPTION STEPGMIN in the netlist, or by making the appropriate choice from the PSpice/Edit Simulation Profile… menu command, Options tab). When enabled, the GMIN stepping algorithm is applied after the circuit fails to converge with the power supplies at 100 percent, and if GMIN stepping also fails, the supplies are then cut back to almost zero and then stepped up.