Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital device modeling October 2019 380 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. JKFF DFF SRFF DLTCH J-K, negative-edge triggered D-type, positive-edge triggered S-R gated latch D gated latch Pullup/pulldown resistors PULLUP PULLDN pullup resistor array pulldown resistor array Delay lines DLYLINE delay line Programmable logic arrays PLAND PLOR PLXOR PLNAND PLNOR PLNXOR PLANDC PLORC PLXORC PLNANDC PLNORC PLNXORC AND array OR array exclusive OR array NAND array NOR array exclusive NOR array AND array, true and complement OR array, true and complement exclusive OR array, true and complement NAND array, true and complement NOR array, true and complement exclusive NOR array, true and complement Table 7-1 Digital primitives summary Type Description