Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital worst-case timing analysis October 2019 660 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Propagation of timing ambiguity As signals propagate through the circuit, ambiguity is contributed by each primitive having a nonzero MIN/MAX delay spread. Consider the following example that uses the delay values of the previous BUF model. Figure 16-2 Timing ambiguity example two. This accumulation of ambiguity may have adverse effects on proper circuit operation. In the following example, consider ambiguity on the data input to a flip-flop. Figure 16-3 Timing ambiguity example three. The simulator must predict an X output, because it is not known with any certainty when the data input actually made the 0-1 transition. If the cumulative ambiguity present in the data signal had been less, the 1 state would be latched up correctly. Figure 16-4 illustrates the case of unambiguous data change (settled before the clock could transition) being latched up by a clock signal with some ambiguity. The Q output will change, but the time of its transition is a function of both the clock's ambiguity and that contributed by the flip-flop MIN/MAX delays. Figure 16-4 Timing ambiguity example four. 5 20 45 35 85 Q D C Q D C