Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital worst-case timing analysis October 2019 670 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. variables)—particularly those due to X states (such as critical hazards)—to determine their cause. Starting at those points, use the waveform analyzer and the circuit schematic to trace back through the network. Continue until you find the reason for the hazard. After you identify the appropriate paths and know the relative timing of the paths, you can do either of the following: ■ Modify the stimulus (in the case of a simple convergence hazard) to rearrange the relative timing of the signals involved. Note: Modifying the stimulus is not generally effective for reconvergent hazards, because the problem is between the source of the reconvergent fanout and the location of the hazard. In this case, discounting the common ambiguity did not preclude the hazard. ■ Change one or both of the path delays to rearrange the relative timing, by adding or removing logic, or by substituting component types with components that have different delay characteristics. In the case of the cumulative ambiguity hazard, the most likely solution is to shorten the path involved. You can do this in either of two ways: ■ Add a synchronization point to the logic, such as a flip-flop—or gating the questionable signal with a clock (having well-controlled ambiguity)—before its ambiguity can grow to unmanageable duration. ■ Substitute faster components in the path, so that the buildup of ambiguity happens more slowly.