Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice A/D User Guide Setting up analyses and starting simulation October 2019 448 Product Version 17.4-2019 © 2022 All Rights Reserved. Caution If you set the user-defined prefix for net to off and make changes to the schematic, the PSpice names might change. Passing parameters to subcircuits Hierarchical netlists have the advantage of allowing parameters to be passed from the top level schematic to any subcircuit schematics. To take advantage of this feature, you must use the new SUBPARAM part in the SPECIAL.OLB library in Capture and you must use the VHDL_DECS part in the STANDARD library in Design Entry HDL. Note: Hierarchical netlists do not support cross-probing from a subcircuit, nor do they support probe markers in a subcircuit. With the SUBPARAM part in Capture or the VHDL_DECS part in Design Entry HDL, you can pass parameters from the top-level schematic to a subcircuit schematic. This allows you to explicitly define the properties and default values to be used during netlisting and simulation. To set up parameter passing to a subcircuit using SUBPARAM in Capture 1. Make the subcircuit your active schematic page in the Capture editor. 2. From the Place menu, choose the Part command. 3. Select the part SUBPARAM from the PSpice library SPECIAL.OLB and place it on the subcircuit. 4. With the SUBPARAM part still selected, from the Edit menu, choose Properties. The Property Editor spreadsheet appears. 5. In the spreadsheet, define the names and default values for the properties that can be changed on an instance-by-instance basis. 6. In the top-level schematic, use the Property Editor spreadsheet to edit the properties of the hierarchical part or block that