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PSpice User Guide Digital worst-case timing analysis October 2019 669 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. network to observe the timing relationships among various devices and make adjustments to the design. Digital worst-case timing simulation does not yield such results without an applied stimulus; it is not a static timing analysis tool. The level of confidence that you establish for your design's timing-dependent characteristics is directly a function of the applied stimulus. Generally, the most productive way to define a stimulus is to use functional testing: a stimulus designed to operate the design in a normal manner, exercising all of the important features in combination with a practical set of data. For example, if you were designing a digital ADDER circuit, you would probably want to ensure that no timing race conditions existed in the carry logic. Your timing simulation methodology should include these key steps: ■ Accurate specification of device delay characteristics. ■ Functional specification of circuit behavior, including all "don't care" states or conditions. ■ A set of stimuli designed to verify the operation of all functions of the design. One common design verification strategy is stepwise identification of the sections of the design that are to be exercised by particular subsets of the stimulus, followed by verification of the response against the functional specification. Complete this phase using normal (not digital worst-case) simulation, with typical delays selected for the elements. The crucial metric here is the state response of the design. Note that (with rare exception) this response consists of defined states and does not include X's. The second phase of design verification is to use digital worst-case simulation, reapplying the functionally correct stimulus, and comparing the resulting state response to that obtained during normal simulation. For example, in the case of a convergence or reconvergence hazard, look for conflicting rise/fall inputs. In the case of cumulative ambiguity, look for successive ambiguity regions merging within two edges forming a pulse. Investigate differences at primary observation points (such as circuit outputs and internal state