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PSpice User Guide Digital worst-case timing analysis October 2019 666 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. In the event that discounting the common ambiguity does not preclude latching the X (or, in the case of simple gates, predicting a glitch), the situation is called a reconvergence hazard. This is the same as a convergence hazard with the conflicting signal ambiguities having a common origin. To use digital worst-case simulation effectively, find the areas of the circuit where signal timing is most critical and use constraint checkers where appropriate. These devices identify specific timing violations, taking into account the actual signal ambiguities (resulting from the elements' MIN/MAX delay characteristics). See the online PSpice Reference Guide for more information about digital primitives. The most common areas of concern include: ■ data/clock signal relationships ■ clock pulse-widths ■ bus arbitration timing Signal ambiguities that converge (or reconverge) on wired nets or buses with multiple drivers may also produce hazards in a manner similar to the behavior of logic gates. In such cases, PSpice A/D factors out any common ambiguity before reporting the existence of a hazard condition. The use of constraint checkers to validate signal behavior and interaction in these areas of your design identifies timing problems early in the design process. Otherwise, a timing-related failure is only identifiable when the circuit does not produce the expected simulation results. See Methodology on page 668 for information on digital worst-case timing simulation methodology.