Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital worst-case timing analysis October 2019 665 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Reconvergence hazard PSpice A/D recognizes situations where signals having a common origin reconverge on the inputs of a single device. In Figure 16-11, the relative timing relationship between the two paths (U2, U3) is important. Figure 16-11 Reconvergence hazard example one. Given the delay values shown, it is impossible for the clock to change before the data input, since the MAX delay of the U2 path is smaller than the MIN delay of the U3 path. In other words, the overlap of the two ambiguity regions could not actually occur. PSpice A/D recognizes this type of situation and does not produce the overly pessimistic result of latching an X state into the Q-output of U4. This factors out the 15 nsec of common ambiguity attributed to U1 from the U2 and U3 signals (see Figure 16-12). Figure 16-12 Reconvergence hazard example two. The result in Figure 16-12 does not represent what is actually propagated at U2 and U3, but is a computation to determine that U2 must be stable at the earliest time U3 might change. This is why an X level should not be latched. 55 90 t=0 15 30 Q D C 25 60 TPLHMN=15 TPLHMX=30 TPLHMN=40 TPLHMX=60 TPLHMN=10 TPLHMX=30 U1 U3 U2 U4 25 45 55 75 U2 U3