Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital worst-case timing analysis October 2019 661 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Identification of timing hazards Timing hazard is the term applied to situations where the response of a device cannot be properly predicted because of uncertainty in the arrival times of signals applied to its inputs. For example, Figure 16-5 below shows the following signal transitions (0-1, 1-0) being applied to the AND gate. Figure 16-5 Timing hazard example. The state of the output does not (and should not) change, since at no time do both input states qualify the gate, and the arrival times of the transitions are known. Convergence hazard In cases where there are ambiguities associated with the signal transitions 0-R-1 and 1-F-0—which have a certain amount of overlap—it is no longer certain which of the transitions happens first. The output could pulse (0-1-0) at some point because the input states may qualify the gate. On the other hand, the output could remain stable at the 0 state. This is called a convergence hazard because the reason for the glitch occurrence is the convergence of the conflicting ambiguities at two primitive inputs. Gate primitives (including LOGICEXP primitives) that are presented with simultaneous opposing R and F levels may produce a pulse of the form 0-R-0 or 1-F-1. For example, a two-input AND gate with the inputs shown in Figure 16-6 below, produces the output shown. Figure 16-6 Convergence hazard example.