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PSpice A/D User Guide October 2019 667 Product Version 17.4-2019 © 2022 All Rights Reserved. 16 Digital worst-case timing analysis This chapter deals with worst-case timing analysis and includes the following sections: ■ Digital worst-case timing on page 667 ■ Starting digital worst-case timing analysis on page 670 ■ Simulator representation of timing ambiguity on page 670 ■ Propagation of timing ambiguity on page 672 ■ Identification of timing hazards on page 673 ■ Convergence hazard on page 673 ■ Critical hazard on page 674 ■ Cumulative ambiguity hazard on page 675 ■ Reconvergence hazard on page 677 ■ Glitch suppression due to inertial delay on page 679 ■ Methodology on page 680 Digital worst-case timing Manufacturers of electronic components generally specify component parameters (such as propagation delays in the case of logic devices) as having tolerances. These are expressed as either an operating range, or as a spread around a typical operating point. The designer then has some indication of how much deviation from typical one might expect for any of these particular component delay values.