Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital worst-case timing analysis October 2019 662 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. This output (0-R-0) should be interpreted as a possible single pulse, no longer than the duration of the R level. Note: Other types of primitives, such as flip-flops, may produce an X instead of an R-0 or F-1 in response to a convergence hazard. The actual device's output may or may not change, depending on the transition times of the inputs. Critical hazard It is important to note that the glitch predicted could propagate through the circuit and may cause incorrect operation. If the glitch from a timing hazard becomes latched up in an internal state (such as flip-flop or ram), or if it causes an incorrect state to be latched up, it is called a critical hazard because it definitely causes incorrect operation. Otherwise, the hazard may pose no problem. Figure 16-7 below shows the same case as above, driving the data input to a latch. Figure 16-7 Critical hazard example. As long as the glitch always occurs well before the leading edge of the clock input, it will not cause a problem. Q D C