Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital device modeling October 2019 388 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. The minimum data-to-clock setup time on a flip-flop is specified as the parameter TSUDCLKMN. Several timing models are used by digital device 74393 from the model libraries. One of them, D_393_1, is shown below for an edge-triggered flip-flop. .model D_393_1 ueff ( + tppcqhlty=18ns tppcqhlmx=33ns + tpclkqlhty=6ns tpclkqlhmx=14ns + tpclkqhlty=7ns tpclkqhlmx=14ns + twclkhmn=20ns twclklmn=20ns + twpclmn=20ns tsudclkmn=25ns + ) When creating your own digital device models, you can create Timing models like these for the primitives you are using. PSpice recommends that you save these in your own custom model library, which you can then configure for use with a given design. One or more parameters may be missing from the Timing model definition. Data books do not always provide all three (minimum, typical, and maximum) timing specifications. The way the simulator handles missing parameters depends on the type of parameter. For a description of Timing model parameters, see the specific primitive type under U devices in the online PSpice Reference Guide. Treatment of unspecified propagation delays Often, only the typical and maximum delays are specified in data books. If, in this case, the simulator were to assume that the unspecified minimum delay defaults to zero, the logic in certain circuits could break down. For this reason, the simulator provides two configurable options, DIGMNTYSCALE and DIGTYMXSCALE, which are used to extrapolate unspecified propagation delays in the Timing models. Note: This discussion applies only to propagation delay parameters (TP). All other timing parameters, such as setup/hold times and pulse widths are handled differently, and are discussed in the following section.