Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice A/D User Guide October 2019 883 Product Version 17.4-2019 © 2022 All Rights Reserved. D data collection, limiting 722 data collection, limiting file size 722 DC analyses displaying simulation results 101 see also DC sweep analysis, bias point detail analysis, small-signal DC transfer analysis, DC sensitivity analysis DC sensitivity analysis 426, 499 introduction 36 DC stimulus property 489 DC sweep analysis 426, 484 to 492 about 485 curve families 491 example 99 introduction 36 nested 489 setting up 99 stimulus 488 DELAY stimulus property (digital) 628 derivative problems 850 design preparing for simulation 43, 140 Design Entry HDL library structure 63 to 69 local (design) libraries 67 reference libraries 65 simulate a design from within 97 views 67, ?? to 68 Design Templates 93 DESIGN_NAME.MAP 48 DESIGN_NAME.NET 47 DESIGN_NAME-ROOT_SCHEMATIC_NA ME.NET 47 DESIGN_NAME-ROOT_SCHEMATIC_NA ME-PROFILE_NAME.SIM.CIR 48 device noise 514, 517 Device types characteristic curves-based 212 template-based 216 device types breakout parts 157 E and G devices 363 Model Editor 212, 216 passive parts 156 PSpice-equivalent parts 362 three- and four-terminal 436 devices, see parts or models diagnostic problems 851 dialog box Advanced Analog Options 441 Arguments for Measurement Evaluation 793 Display Control (Probe) 705 Display Measurement Evaluation 797 Measurements 792 Simulation Message Summary 765 Traces for Measurement Arguments 794 DIG_GND stimulus property (digital) 629 DIG_PWR stimulus property (digital) 629 DIGDRVF (strengths) 406 DIGDRVZ (strengths) 406 DIGERRDEFAULT (simulation option) 648 DIGERRLIMIT (simulation option) 648 DIGIOLVL (simulation option) 393 digital device modeling 383 to 420 digital primitives list ?? to 389 digital primitives syntax 390 to ?? example "U" device declaration 393 functional behavior 385 inertial delay 399 input/output characteristics 401 to 411 AtoD and DtoA subcircuits 408 charge storage on nets 407 configuring the strength scale 405 controlling overdrive 406 defining output strengths 404 I/O model 401 I/O model parameters 403 internal delay functions 398 overview 384 propagation delay calculation 398 timing characteristics 395 to 400 timing model 395 unspecified propagation delays unspecified timing constraints 397 transport delay 400 digital primitives see also parts input (N device) 408 output (O device) 408 propagation delays, see timing model syntax 390 timing model, see timing model digital signals, see traces digital simulation ?? to 649 adding digital trace expressions 639