Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice A/D User Guide Digital simulation October 2019 646 Product Version 17.4-2019 © 2022 All Rights Reserved. Simulation condition messages PSpice A/D produces warning messages in various situations, such as those that originate from the digital CONSTRAINT devices monitoring timing relationships of digital nodes. These messages are directed to the simulation output file and/or to the waveform data file. Options are available for controlling where and how many of these messages are generated, as summarized later in this section. Table 14-12 below summarizes the simulation message types, with a brief description of their meaning. Currently, the messages supported are specific to digital device timing violations and hazards. Table 14-12 Simulation condition messages—timing violations Message type Severity level Meaning SETUP WARNING Minimum time required for a data signal to be stable prior to the assertion of a clock was not met. HOLD WARNING Minimum time required for a data signal to be stable after the assertion of a clock was not met. RELEASE WARNING Minimum time required for a signal that has gone inactive (usually a control such as CLEAR) to remain inactive before the asserting clock edge was not met. WIDTH WARNING Minimum pulse width specification for a signal was not satisfied; that is, a pulse that was too narrow was observed on the node. FREQUENCY WARNING Minimum or maximum frequency specification for a signal was not satisfied. Minimum frequency violations indicate that the period of the measured signal is too long, while maximum frequency violations describe signals changing too rapidly. GENERAL INFO Boolean expression described within the GENERAL constraint checker was evaluated and produced a true result.