PSpice User Guide

PSpice User Guide

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PSpice User Guide Things you need to know October 2019 64 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Figure 1-5 Directory structure of Design Entry HDL Libraries library\ library1\ <>.cat cell\ sym_1\ symbol.css, master.tag sym_2\ symbol.css, master.tag sym_3\ symbol.css, master.tag chips\ chips.prt, master.tag part_table\ template_ptf.txt, master.tag .ptf vlog_model\ verilog.v, master.tag swift_model\ verilog.v, master.tag awb_model\ model.sp, device.prp, master.tag vlog_rtl_model\ verilog.v, master.tag sch_1\ page1.csa, page1.csc master.tag entity\ verilog.v, vhdl.vhd, pc.db vlog004u.sir, master.tag doc_1\ doc1.csa, doc1.csb, master.tag vlog_map\ verilog map master tag cdssetup\cds.lib \share\

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