Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice A/D User Guide Digital device modeling October 2019 392 Product Version 17.4-2019 © 2022 All Rights Reserved. Figure 7-1 Elements of a digital device definition MNTYMXDLY is an optional device parameter that selects either the minimum, typical, or maximum delay values from the device's timing . subckt DotA_STD D A DPWR DGND + params: DRVL=0 DRVH=0 CAPACITANCE=0 N1 A DGND DPWR DIN74 DGTLNET=D IO_STD C1 A DGND {CAPACITANCE+0.1pF} .ends .subckt AtoD_STD A D DPWR DGND + .params: CAPACITANCE=0 O0 A DGND DO74 DGTLNET=D IO_STD C1 A DGND {CAPACITANCE+0.1pF} .ends .subckt 7400 A B Y + params: MNTYMXDLY=0 IO_LEVEL=0 + optional: DPWR=$G_DPWR DGND=$G_DGND U1 NAND(2) DPWR DGND A B Y + D_7400 IO_STD + MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL} .model IO_STD uio ( + drvh=96.4 drvl=104 + AtoD1="AtoD_STD" AtoD2="AtoD_STD_NX" + AtoD3="AtoD_STD" AtoD4="AtoD_STD_NX" + DtoA1="DtoA_STD" DtoA2="DtoA_STD" + DtoA3="DtoA_STD" DtoA4="DtoA_STD" + tswhl1=1.373ns tswlh1=3.382ns ... + DIGPOWER="DIGIFPWR" ) DtoA interface subcircuit AtoD interface subcircuit I/O model .model D_7400 ugate ( + tplhty=11ns tplhmx=22ns + tphlty=7ns tphlmx=15ns ) Digital device Timing model .model DO74 doutput( + s0name="X" s0vlo=0.8 s0vhi=2.0 + s1name="0" s1vlo=0.0 s1vhi=0.8 + s2name="R" s2vlo=0.8 s2vhi=1.4 + s3name="R" s3vlo=1.3 s3vhi=2.0 + s4name="X" s4vlo=0.8 s4vhi=2.0 + s5name="1" s5vlo=2.0 s5vhi=7.0 + s6name="F" s6vlo=1.3 s6vhi=2.0 + s7name="F" s7vlo=0.8 s7vhi=1.4 + ) .model DIN74 dinput( + s0name="0" s0tsw=3.5ns s0rlo=7.13 s0rhi=389 + s1name="1" s1tsw=5.5ns s1rlo=467 s1rhi=200 + s2name="X" s2tsw=3.5ns s2rlo=42.9 s2rhi=116 + s3name="R" s3tsw=3.5ns s3rlo=42.9 s3rhi=116 + s4name="F" s4tsw=3.5ns s4rlo=42.9 s4rhi=116 + s5name="Z" s5tsw=3.5ns s5rlo=200K s5rhi=200K + ) Digital input (DtoA) model Digital output (AtoD) model