Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital device modeling October 2019 390 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. ■ If the maximum value is omitted, it takes on the typical value if one was specified, otherwise it takes on the minimum value. ■ If the typical value is omitted, it is computed as the average of the minimum and maximum values. Propagation delay calculation The timing characteristics of digital primitives are determined by both the timing models and the I/O models. Timing models specify propagation delays and timing constraints such as setup and hold times. I/O models specify input and output loading, driving resistances, and switching times. When a device's output connects to another digital device, the total propagation delay through a device is determined by adding the loading delay (on the output terminal) to the delay specified in the device's timing model. Loading delay is calculated from the total load on the output and the device's driving resistances. The total load on an output is found by summing the output and input loads (OUTLD and INLD in the I/O model) of all devices connected to that output. This total load, combined with the device's driving resistances (DRVL and DRVH in the I/O model), allows the loading delay to be calculated: Loading delay = R DRIVE ·C TOTAL ·ln(2) The loading delay is calculated for each output terminal of every device before the simulation begins. The total propagation delay is easily calculated during the simulation by adding the pre-calculated loading delay to the device's timing delay. However, for any individual timing delay specification (e.g., TPLH) having a value of 0, the loading delay is not used. When outputs connect to analog devices, the propagation delay is reduced by the switching times specified in the I/O model. See Input/Output characteristics on page 393 for more information. Inertial and transport delay The simulator uses two different types of internal delay functions when simulating the digital portion of the circuit: inertial delay and transport delay. The application of these concepts is embodied