Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Mixed analog/digital simulation October 2019 653 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. The lines that begin with "Moving…from analog node" indicate the new digital node names that were generated. Below each of these are the interface subcircuit calls inserted by PSpice A/D. In this example, the subcircuits named AtoD_STD and DtoA_STD are obtained from the I/O model that is referenced by the inverter primitive inside the subcircuit describing the 7404 part. The CAPACITANCE, DRVL (low-level driving resistance), and DRVH (high-level driving resistance) subcircuit parameter values come from the same I/O model. After the interface subcircuit calls, PSpice A/D inserts one or more interface power supply subcircuits. The subcircuit name is specified in the I/O model for the digital primitive at the interface. In this example, PSpice A/D inserted DIGIFPWR, which is the power supply subcircuit used by all TTL models in the model library. DIGIFPWR creates the global nodes $G_DPWR and $G_DGND, which are the default nodes used by each TTL part. **** Generated AtoD and DtoA Interfaces **** * * Analog/Digital interface for node 1 * * Moving X1.U1:.A from analog node 1 to new digital node * 1$AtoD X$1_AtoD1 1 1$AtoD $G_DPWR $G_DGND AtoD_STD + PARAMS: CAPACITANCE= 0 * Moving X2.U1:.A from analog node 1 to new digital node * 1$AtoD2 X$1_AtoD2 1 1$AtoD $G_DPWR $G_DGND AtoD_STD + PARAMS: CAPACITANCE= 0 * * Analog/Digital interface for node 2 * ** Moving X1.U1.Y from analog node 2 to new digital node * 2$DtoA X$2_DtoA1 2$DtoA 2 $G_DPWR $G_DGND DtoA_STD + PARAMS: DRVL=0 DRVH=0 CAPACITANCE=0 * * Analog/Digital interface power supply subcircuit * X$DIGIFPWR 0 DIGIFPWR .END ;(end of AtoD and DtoA interfaces) Figure 15-2 Simulation output for mixed analog/digital circuit.