Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital simulation October 2019 632 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Tracking timing violations and hazards When there are problems with your design, such as setup/hold violations, pulse-width violations, or worst-case timing hazards, PSpice A/D saves messages to the simulation output file or data file. You can select messages and have the associated waveforms and detailed message text automatically appear. The messaging feature is discussed further in Tracking digital simulation messages on page 752 of Chapter 17, "Analyzing waveforms." PSpice A/D can also detect persistent hazards that may have a potential effect on a primary circuit output or on the internal state of the design. Persistent hazards Digital problems are usually either timing violations or timing hazards. Timing violations include SETUP, HOLD and minimum pulse WIDTH violations of component specifications. This type of violation may produce a change in the state behavior of the design, and potentially in the answer. However, the effects of many of these errors are short-lived and do not influence the final circuit results. For example, consider an asynchronous data change on the input to flip-flop FF1 in Figure 14-2 below. The data change is too close to the clock edge e1, resulting in a SETUP violation. In a hardware implementation, the output of FF1 may or may not change. However, some designs are not sensitive to this individual missed data because the next clock edge (e2 in this example) latches the data. The designer must judge the significance of timing errors, accounting for the overall behavior of the design. ... ... e1 e2 D C Q ~Q D C Q ~Q FF1 FF2 O1 O2 O3 S Figure 14-2 Circuit with a timing error.