Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide Digital simulation October 2019 623 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Selecting propagation delays All digital devices—including primitives and library models—perform simulations using either minimum, typical, maximum or worst-case (min/max) timing characteristics. You can set the delay circuit-wide or on individual device instances. Circuit-wide propagation delays You can set these to minimum, typical, maximum or variable within the min/max range for digital worst-case timing simulation on the Options tab of the Simulation Settings dialog box. To specify the delay level circuit-wide 1. From Capture's PSpice menu, choose Edit Simulation Profile. 2. Click the Options tab. 3. In the Category list box, select Gate-level simulation. Part instance propagation delays You can set the propagation delay mode on an individual device, thereby overriding the circuit-wide delay mode. To override the circuit-wide default on an individual part 1. Set the part's MNTYMXDLY property from 1 to 4 where By default, MNTYMXDLY is set to 0, which tells PSpice A/D to use the circuit-wide value defined in the Options tab. 1 = minimum 2 = typical 3 = maximum 4 = worst-case (min/max)