Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice A/D User Guide Digital device modeling October 2019 418 Product Version 17.4-2019 © 2022 All Rights Reserved. where the value of DIGMNTYSCALE is between 0.1 and 1.0 with the default value being 0.4. If the typical is known and the maximum is not, then the simulator uses the formula: TPxxMX = DIGTYMXSCALE X TPxxTY where the value of DIGTYMXSCALE is greater than 1.0 with the default being 1.6. If the typical value is not known, and both the minimum and maximum are, then the typical value used by the simulator will be the average of the minimum and maximum propagation delays. If only one of min or max is known, then the typical delay is calculated using the appropriate formula as listed above. If all three are unknown, then they all default to a value of 0. Constraint checker (CONSTRAINT primitive) The CONSTRAINT primitive provides a general constraint checking mechanism to the digital device modeler. It performs setup and hold time checks, pulse width checks, frequency checks, and includes a general mechanism to allow user-defined conditions to be reported. See the Digital Devices chapter in the PSpice A/D Reference Guide for more information. Setup_Hold The expressions in the SETUP_HOLD specification may be listed in any order. CLOCK defines the node that is to be used as the reference for the setup/hold/release specification. The assertion edge must be LH or HL (for example, a transition from logic state 0 to 1 or from 1 to 0.) DATA specifies which node(s) is to have its setup/hold time measured. SETUPTIME defines the minimum time that all DATA nodes must be stable prior to the assertion edge of the clock. The time value must be a nonnegative constant or expression and is measured in seconds. If the device has different setup/ hold times depending on whether the data is HI or LOW at the clock change, you can use either or both of the following forms: