Issue link: https://resources.pcb.cadence.com/i/1180526
PSpice User Guide
Digital device modeling
October 2019 400 Product Version 17.4-2019
© 1999-2019 All Rights Reserved.
The I/O model parameters INR, DRVZ, and TSTOREMN (see
Table 7-2 on page 395) are used by the simulator to determine which
nets should be simulated as charge storage nets. The simulator will
simulate charge storage only for a net which has some devices
attached to it which can be high impedance (Z), and which has a
storage time greater than or equal to the smallest TSTOREMN of all
inputs attached to the net. The storage time is calculated as the total
capacitance (sum of all INLD and OUTLD values for attached inputs
and outputs) multiplied by the total leakage resistance for the net (the
parallel combination of all INR and DRVZ values for attached inputs
and outputs).
Note: The default values provided by the UIO model will not allow
the use of charge-storage simulation techniques—even with circuits
using non-PSpice libraries of digital devices. This is appropriate,
since these libraries are usually for PCB-based designs.
Creating your own interface subcircuits for
additional technologies
If you are creating custom digital parts for a technology which is not
in the model libraries, you may also need to create AtoD and DtoA
subcircuits. The new subcircuits need to be referenced by the I/O
models for that technology. The AtoD and DtoA interfaces have
specific formats, such as node order and parameters, which are
expected by PSpice for mixed-signal simulations.
If you are creating parts in one of the logic families already in the
model libraries, you should reference the existing I/O models
appropriate to that family. The I/O models, in turn, automatically
reference the correct interface subcircuits for that family. These, too,
are already contained in the model libraries.
The AtoD interface subcircuit format is shown here:
.SUBCKT ATOD