Issue link: https://resources.pcb.cadence.com/i/1180190
Migration Guide for Allegro Platform Products Allegro Platform Package Products October 2019 114 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. Note: For other changes, see the Core Allegro Platform Back-End Products chapter. Migrating to Release 16.6 Logic commands for co-design components For co-design components in a design, all logic commands such as assign net, deassign net, swap, auto assign, and auto create are enhanced in 16.6 to retain logic connectivity. What this means is, compared to 16.5 where only nets were updated with logic commands, in 16.6 net association with the function pin is retained while performing edits with logic commands. Note: You can enable 16.5 behavior by setting the logic_edit_enabled option in User Preferences. Mixed-Case Support and Co-Design Option in Verilog from SCM The verilog generated by SCM supports mix-case port and module names in 16.6. In the earlier releases only lower-case names were supported. In addition, there is a new Mark as co-design option in import verilog form. Wire Bond Application Mode Replaces the wirebond select Command A new application mode has been added for wire bond operations. You can select this mode by choosing Setup – Application Mode – Wire Bond Edit, or by clicking the application mode field on the right of the bottom status bar. This application mode replaces the wirebond select command, which will be retired in a future release. New Assembly Rule Checks New Assembly Rule Checks have been added in 16.6 including a new group for cavities and interaction of cavities and other structures. Two existing rules have been updated. The following table describes the constraints: Constraint Name in techfile Design – Acute Angle Metal Acute Angle Routing ADRC_ACUTE_ANGLE_ROUTING