Issue link: https://resources.pcb.cadence.com/i/1180190
Migration Guide for Allegro Platform Products
Allegro Platform Front-End Products
October 2019 12 Product Version 17.4-2019
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Migrating from Release 16.5 to Release 16.6
The following section provides guidelines to migrate designs from 16.5 to the 16.6 release.
Constraint Manager Voltage Net in Electrical Domain
When migrating designs from the 16.5 release to the 16.6 release, the only notable change
is that a voltage net which is a member of a Constraint Manager net, will now be visible in the
electrical domain in Constraint Manager.
Release 16.5 onwards, a signal can be declared a global signal or an interface signal.
However, if you have a signal that is defined as both, global, and interface, it might lead to a
loss of constraints during migration. In such a case, a netlisting error is displayed in releases
16.5 and 16.6.
If you are migrating from a pre-16.5 release to the 16.6 release, refer to the Migrating to
Release 16.5 section. All the changes listed in this section are valid for migrating designs to
the 16.6 release.
Migrating to Release 16.5
The following sections provides guidelines to migrate pre-16.5 designs to the 16.5 release.
■ Design Uprev
■ Changes in Constraint Manager
■ Preparing to Migrate Designs to the 16.5 Release
■ Steps to Migrate Designs to the 16.5 Release
■ Notable Changes in the 16.5 Release
Design Uprev
Architectural changes in the 16.5 release aim to provide DE-HDL with a dynamic connectivity
model. The architectural changes have led to some file changes due to which it is necessary
to uprev existing designs. When you open an earlier design in the 16.5 release, DE-HDL auto-
detects the need for upreving the design. The uprev utility is also available as a batch
command and can be executed on designs without opening DE-HDL.
csnetlister - proj