Issue link: https://resources.pcb.cadence.com/i/1180190
Migration Guide for Allegro Platform Products Core Allegro Platform Back-End Products October 2019 75 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. ■ If a design with embedded geometry is upreved, the Embedded Geometry/Soldermask subclass will be disabled by default. You can enable Embedded_Soldermask from the Embedded Layers Setup tab of the Cross Section Editor dialog box. ■ If an upreved design is used with the new multi-stackup/zones feature, Embedded_Soldermask will be enabled when first stackup is assigned to a zone. ■ Once Embedded_Soldermask is enabled, you do not have an option to disable it. When enabled, new soldermask subclasses are created under Embedded_Geometry and any placed embedded symbols will be updated with embedded soldermask. ■ For new designs or upreved designs with no embedded information Embedded_Soldermask will be included by default. ■ To allow placement of symbols on a zone surface layer (other than Top/Bottom) the Embedded_Geometry subclasses are created for these layers. The layers are not required to be marked embedded. ■ Embedded subclasses cannot be removed, if a layer is: ❑ Converted from embedded to not embedded, and the layer is the Top or Bottom surface of a stackup assigned to a zone. ❑ No longer the Top or Bottom layer of the stack, and the layer is marked embedded in primary or other stackups assigned to a zone. Electrical DRC ■ Changes to the Differential Pair Dynamic Phase DRC algorithm might introduce DRCs after uprev. Phase DRC now checks back to driver pins, formerly the gathering location. To maintain pre-17.2 DRC state for differential pairs, set variable legacy_diffpair_checks.