Migration Guide for Allegro Platform Products
Allegro Platform Front-End Products
October 2019 19 Product Version 17.4-2019
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Notable Changes in the 16.5 Release
After you have migrated your design to the 16.5 release, you will notice the following changes:
■ On launching Constraint Manager, bus names in an unpackaged design remain the
same across the hierarchy. They will not be assigned a unique name. You need to
package the design to assign unique names to the bus and nets.
■ In the 16.5 release, the instance name is followed by the design block name in the
hierarchy viewer. For example, in Page1_i1, the instance name 'page1_i1' is
followed by the block name TOP.
In a pre-16.5 release, the design block name was followed by the instance name: TOP
. In this case, TOP is the design block name followed by the instance name
in the hierarchy viewer.
■ When bits of a bus are aliased with a scalar signal, or with bits of another bus, the bits of
the bus appear only with the winning net name. The bits no longer appear in the original
bus. For example, in a pre-16.5 release, if Bus B had four members, and was aliased with
Bus A, then the bits of the Bus B would have been visible in the winning Bus A as well
as Bus B. In the 16.5 release, only Bus A will be displayed as the winning bus and the
losing Bus B will be displayed as an empty bus.
■ There is a change in the visibility of pin pair names in the 16.5 release. In hierarchical
designs, pin pairs no longer display the complete hierarchical path. For example, in a pre-
16.5 release, pin names for flat designs were displayed as
Pagenumber_instance.Pin_number 1_I1.12, and for hierarchical designs they
were displayed as 1_I3_1_I1.12. In the 16.5 release, pin pair names are displayed as
PAGE1_I1.1 for both, flat, and hierarchical designs.
■ There are changes in the netlisting process in the 16.5 release. As a result of these
changes, the ASSIGN_TMP directive is no longer required for read-only blocks. New 16.5
design projects do not use the ASSIGN_TMP directive. In projects that have been
upreved from 16.3, Design Entry HDL comments out the ASSIGN_TMP directive in
cds.lib.
