Migration Guide for Allegro Platform Products
Allegro Platform Front-End Products
October 2019 13 Product Version 17.4-2019
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csnetlister -proj .cpm -renetlist -library -block
csnetlister -proj test.cpm -renetlist -library test_lib -block top
You can use the following command to uprev all blocks in the design library:
csnetlister -proj test.cpm -renetlist -library test_lib -allblocks
Each hierarchical block in the design is upreved to the 16.5 release. The uprev process does
not modify any of the schematic sheets. However, after migrating your design, you will notice
some changes in the file structure. Two new files, the xcon file and .dcf, are generated in the
sch_1 view. These two files contain information about design connectivity, properties, and
constraints. When DE-HDL auto-detects the need for upreving the design, it searches for
these two files. However, because these files are not included in pre-16.5 designs, DE-HDL
cannot detect them. Therefore, it prompts you to uprev the design.
Changes in Constraint Manager
All constraint information resides in a single file, the *.dcf file. The *.dcf file is stored in the
sch_1 view. As a result, the Constraints view is no longer required.
The *.dcf file now stores properties. As a result, the viewprop.prp file in the sch_1 view, and
the Occurrence Property (*.opf) file in the opf view have been removed.
This table summarizes the changes to the schematic files.
Files in pre-16.5
Releases
Changes 16.5 Release Onwards
master.tag Changed to add xcon and dcf file names
verilog.v Not created /moved to *.bak
viewprps.prp Not created /moved to *.bak
viewprps.prp Not created /moved to *.bak
hdldirect.dat Not created /moved to *.bak
vlog004u.sir Not created /moved to *.bak
design.xcon New file created
design.dcf New file created
