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10 - Options and Data Collection in Simulation Settings

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Use the Options tab of the Simulation Settings dialog box to fine-tune how PSpice performs calculations for PSpice Simulink Co-Simulation, as well as what information to save to the simulation output file (*.OUT):

Analog Simulation Options

Use the Analog Simulation settings to fine-tune analog simulation accuracy, set iteration limits, set operating temperature, and specify MOSFET parameters.

In the Simulation Settings dialog box, the option names shown before the text box correspond to the option names used in the PSpice .OPTIONS command. For more information about this command, refer to the PSpice Reference Guide.

Click this option… To do this…
General Enter values for speed level, tolerances, and minimum conductance.
Auto Converge Suggest relaxed limits for various options Click this...that PSpice can modify during a simulation to achieve convergence.
MOSFET Option Enter values for the default drain area, default source area, default length, and default width.

The following tables defines all the options for the Analog Simulation category:

Flag options in Analog Simulation Meaning
ADVCONV Enables all convergence algorithms, such as Pseudo Tran, STEPGMIN, and step sources. ON by default.
AutoConverge Suggest relaxed limits for various options that PSpice can modify during a simulation to achieve convergence.
Restart Restart the convergence calculation
PREORDER Presorts the matrix diagonal by Markowitz counts.
Options Description Units Default
General
SPEED_LEVEL increases simulation performance by optimizing switching behavior of models. If increase in simulation performance is not needed, set SPEED_LEVEL=0. - 3
RELTOL relative accuracy of V and I 0.001
VNTOL best accuracy of voltages volt 1.0 uV
ABSTOL best accuracy of currents amp 1.0 pA
CHGTOL best accuracy of charges coulomb 0.01 pC
GMIN minimum conductance used for any branch ohm-1 1.0E-12
ITL1 Maximum number of iterations of convergence calculation during bias point analysis 150.0
ITL2 Maximum number of iterations of convergence calculation during DC analysis 20
ITL4 Maximum number of iterations of convergence calculation at each time step during transient analysis 10
TNOM Nominal Temperature value Celsius 27 degrees Celsius
THREADS maximum number of threads. Set to 0 for engine default. THREADS=1 implies single-thread. Number of cores/2
Auto Converge
ITL1, ITL2, ITL4, RELTOL, ABSTOL, VNTOL Same as General section
PIVTOL absolute magnitude required for pivot in matrix solution 1.0E-13
MOSFET Option
DEFAD MOSFET default drain area (AD). meter2 0.0
DEFAS MOSFET default source area (AS). meter2 0.0
DEFL MOSFET default length (L). meter 100.0 u
DEFW MOSFET default width (W). meter 100.0 u

Analog Advanced Options

Use the Analog Advanced settings to enter values for the total transient iteration limit, relative magnitude for matrix pivot, and absolute magnitude for matrix pivot.

In the Simulation Settings dialog box, the option names shown before each text box correspond to the option names used in the PSpice .OPTIONS command. For more information about this command, refer to the PSpice Reference Guide.

Click this... To do this…
General Enter values for speed level, tolerances, and minimum conductance.
Bias Point Suggest relaxed limits for various options that PSpice can modify during a simulation to achieve convergence.
Transient Enter values for the default drain area, default source area, default length, and default width.

The following tables defines all the options in the tab for the Analog Advanced category:

Flag option for Analog Advanced Meaning
NOGMINI Specifies not to add GMIN across current sources.
BRKDEPSRC Sets automatic break-points for behavioral sources.
CONVAID Generates .1OP file for debugging purpose when convergence fails.
STEPGMIN Enables GMIN stepping. This causes a GMIN stepping algorithm to be applied to circuits that fail to converge. GMIN stepping is applied first, and if that fails, the simulator falls back to supply stepping.
NOSTEPSRC Do not run source stepping algorithm for bias point convergence.
NOSTEPDEP Do not step dependent sources during source stepping algorithm for bias point convergence.
GMINSRC Enables step GMIN inside source-stepping
PSEUDOTRAN Uses Pseudo-Transient Method
TRANCONV Enables alternate path search if transient simulation fails.
Options Description Units Default
General
ITL5 total repeating limit for all points for transient analysis
( ITL5 =0 means ITL5 =infinity)		 - 0.0
PIVREL relative magnitude required for pivot in matrix solution - 1.0E-3
PIVTOL absolute magnitude required for pivot in matrix solution - 1.0E-13
SOLVER performance package solution algorithm
(Solver = 0 selects the original solution algorithm;
Solver = 1 selects the advanced solution algorithm)		 - 1
DMFACTOR Sets the relative factor for minimum delta. The value specifies the relative value by which the minimum time step size is changed. The value should be less than or equal to 1 and a factor of 10, such as .1, .001, or .0001.
WCDEVIATION worst case deviation. It can have double values between 0 and 1. - Same as RELTOL
LIMIT the absolute voltage limit. The default, 0, specifies that there is no limit on data values. You can modify it to a large value, such as 1e12, to eliminate overflow errors, especially when using exponential sources. - 0
DIODECJO Minimum value for Diode junction capacitance ohm 0
DIODERS Minimum value for Diode ohmic resistance ohm 0
BJTCJ minimum value for BJT Base-collector zero-bias depletion capacitance (Cjc), Base-emitter zero-bias depletion capacitance (Cje), and zero-bias collector substrate capacitance (Cjs) farad 0
Bias Point
GMINSTEPS the GMIN stepping size in integer (any positive value). Set to 0 for engine default. - Same as ITL1
ITL6 the number of steps of the source stepping algorithm. Can have any positive integer value. Set to 0 for engine default. - Same as ITL1
PTRANSTEP number of steps for a pseudo transient analysis to find the operating point. Can be any positive integer value. Set to 0 for engine default. - Same as ITL1
Transient
METHOD integration method
(values can be either TRAPEZOIDAL or GEAR)		 - -
TRTOL tolerance for integration error calculated using transient analysis. It is a relative tolerance where a higher TRTOL value results in bigger time steps and reduced accuracy. The TRTOL value should NOT be greater than 1/RELTOL. - 7
CSHUNT shunt capacitance added from all nodes of the design to GND. Recommended value is 1pF. farad 0

Gate Level Simulation Options

Use the Gate Level Simulation settings to set timing, I/O levels for interfaces, drive strength, and error message limits.

Click this… To do this…
General Enter values to set delay or initial state in flip-flops or latches.
Advanced Enter values for the minimum output drive resistance, maximum output drive resistance, overdrive ratio, default delay calculation, and error message limits.

The following tables defines all the options for the Gate Level Simulation category:

Flag option for Gate Level Simulation Meaning
NOPRBMSG Suppresses simulation error messages in Probe data file.
Options Description Units Default
General
DIGMNTYMX default delay selector: 1=min, 2-typical, 3=max, 4=min/max - 2.0
DIGINITSTATE sets initial state of all flip-flops and latches in circuit: 0=clear, 1=set, 2=X - 2.0
DIGIOLVL default digital I/O level: 1-4; - 1.0
Advanced
DIGDRVF minimum drive resistance
(Input/Output UIO type model, DRVH (high) and DRVL (low) values)		 ohm 2.0
DIGDRVZ maximum drive resistance
(UIO type model, DRVH and DRVL values)		 ohm 20K
DIGOVRDRV ratio of drive resistances required to allow one output to override another driving the same node - 3.0
DIGMNTYSCALE scale factor used to derive minimum delays from typical delays - 0.4
DIGTYMXSCALE scale factor used to derive maximum delays from typical delays - 1.6
DIGERRDEFAULT default error limit per digital constraint device - 20.0
DIGERRLIMIT maximum digital error message limit - 0

Output File Options

Use the Output File settings to select the types of information PSpice saves to the simulation output file.

The following table defines all the options for the Output File category:

Flag option for Output File Meaning
ACCT Summary and accounting information is printed at the end of all the analyses (refer to your PSpice User’s Guide for further information on ACCT).
EXPAND Lists devices created by subcircuit expansion and lists contents of the bias point file.
LIBRARY Lists lines used from library files.
LIST Lists a summary of the circuit elements (devices).
NOBIAS Suppresses the printing of the bias point node voltages.
NODE Lists a summary of the connections (node table).
NOECHO Suppresses a listing of the input file(s).
NOMODE Suppresses listing of model parameters and temperature updated values.
NOOUTMSG Suppresses simulation error messages in output file.
NOPAGE Suppresses paging and the banner for each major section of output.
OPTS Lists values for all options.
Options Description Units Default
NUMDGT Number of digits in printed values. This is 4 by default.
WIDTH same as the .WIDTH OUT= statement
(can be set to either 80 or 132)		 Default is 80.

Data collection options for simulation profiles

Use the Data Collection tab of the Simulation Settings dialog box to restrict the captured simulation data. This is especially useful for large circuit designs that produce more data than you need for waveform analysis.

Data Collection Options

Option Description
All All data will be collected and stored.
All but Internal Subcircuits All data will be collected and stored except for internal subcircuits of hierarchical designs (top level data only).
At Markers Only Data will only be collected and stored where markers are placed.
None No data will be collected.

View the next document: 11 - Sample Circuits

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