Skip to main content

24 – Netlist Examples

Published Date

Accel netlist format Algorex netlist format Altera ADF netlist format AppliconBRAVO netlist format AppliconLEAP netlist format Cadnetix netlist format Calay90 netlist format Calay netlist format Case netlist format CBDS netlist format Computervision netlist format DUMP netlist format EDIF 2 0 0 netlist format EEDesigner netlist format Futurenet netlist format HiLo netlist format Intel ADF netlist format Intergraph netlist format Mentor netlist format Multiwire netlist format OHDL netlist format PADS 2000 netlist format PADS PCB netlist format PCAD netlist format PCADnlt netlist format PCBII and PCBIIL netlist formats PDUMP netlist format PLD netlist format Protel2 netlist format RecalRedac netlist format RINF netlist format Scicards netlist format Tango netlist format Telesis netlist format Vectron netlist format Verilog netlist format VHDL netlist format VST Model netlist format WinBoard netlist format WireList netlist format

This chapter provides a brief overview of some of the netlist formats available from Capture.

Accel netlist format

The Accel PCB format netlists from ACCEL Technologies have these characteristics:

  • All ASCII characters are legal.
    For more information, see the ACCEL Technologies website or the Protel website.
Example
(compinst "Y1"
(patternName "10MHz")
(compvalue "10MHz "))
(compinst "Y2"
(patternName "DIP.100/14/W.300/L.800")
(compvalue "24.576MHz"))
(compinst "Y3"
(patternName "4.9152MHz")
(compvalue "4.9152MHz"))
(compinst "Y4"
(patternName "3.6864MHz")
(compvalue "3.6864MHz"))
(net "N03627"
(node "JP5" "26")
(node "R43" "2"))
(net "N08082"
(node "L1" "2")
(node "C8" "1")
(node "L2" "1"))
(net "N03663"
(node "U72" "1")
(node "R53" "2"))
(net "N08139"
(node "L6" "2")
(node "C19" "1")
(node "R20" "1")
(node "C15" "2"))

Algorex netlist format

The Algorex format has these characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers are limited to six digits following the "N" prefix.
  • Pin names are not used.
    All ASCII characters are legal.
Example
GND
U1 (14DIP300)-7,
U2 (14DIP300)-7
VCC
U1 (14DIP300)-14,
U2 (14DIP300)-14
CLOCK
U1 (14DIP300)-10
Q
U1 (14DIP300)-6,
U2 (14DIP300)-2,
U1 (14DIP300)-9
OUT
U2 (14DIP300)-3
B
U1 (14DIP300)-4
N00019
U1 (14DIP300)-3,
U2 (14DIP300)-1
N00013
U1 (14DIP300)-5,
U1 (14DIP300)-8
A
U1 (14DIP300)-1,
U1 (14DIP300)-2

Altera ADF netlist format

The AlteraADF format has these characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • All ASCII characters are legal.
Altera netlist constraints

When you create an AlteraADF netlist, you must include the OrCAD-supplied ALTERA_P.OLB and ALTERA_M.OLB libraries in your project. You can use only the parts in these two libraries to create the schematic design.
Inputs and outputs are handled differently in Capture and the Altera software. Capture defines inputs and outputs with hierarchical ports and library objects. Altera defines inputs and outputs with a library object, which is then tagged with the appropriate pin number. In the example schematic page, the CLOCK signal is an input and the STROBE signal is an output.
Additionally, library objects with unused pins default to predefined levels in the Altera software. Because Capture does not default unconnected pins to any particular level, you must tie all unused pins to the appropriate level.

Altera pipe commands

You can place equations in your schematic folder to be included in the netlist. To place these equations on the schematic page, choose the Text command from the Place menu.
Each equation must start with the pipe character (|). The first line must be:

|EQUATIONS

This tells Capture that some AlteraADF equations need to be included in the netlist. The equations can contain any information you want to include in the netlist.

Altera title block information

Title block information is placed in the first 10 lines of the netlist. The following table shows an example netlist header and the title block information from which the header was extracted. Header information in bold is text entered in the schematic page's title block.

i

Line

Example header

Title block field

1

ADF Example

Title of schematic page

1

May 15, 2002

Date

2

OrCAD-02

Document number

2

A

Revision code

3

OrCAD

Organization name

4

9300 SW Nimbus Avenue

1st Address Line

6

Turbo = ON

3rd Address Line

7

5C031

4th Address Line
Example
ADF Example Revised: Friday, November 13, 1998
OrCAD-02 Revision: A
OrCAD
9300 S.W. Nimbus Ave.
TURBO = ON
5C031
OPTIONS:TURBO = ON
PART:5C031
INPUTS:
CLOCK
ENABLE
COINDROP
CUPFULL
RESET
OUTPUTS:
STROBE
POURDRNK
DROPCUP
NETWORK:
J=INP(ENABLE) % SYM 1 %
N=INP(CUPFULL) % SYM 2 %
O=OR(P,Q) % SYM 3 %
POURDRNK,E=RORF(O,D,H,I,J) % SYM 4 %
Q=AND(F,R) % SYM 5 %
R=NOT(E) % SYM 6 %
B=XOR(E,F) % SYM 7 %
A=AND(B,C) % SYM 8 %
STROBE=CONF(A,VCC) % SYM 9 %
C=NOT(D) % SYM 10 %
D=INP(CLOCK) % SYM 11 %
H=AND(F,E) % SYM 12 %
I=INP(RESET) % SYM 13 %
G=AND(K,L,M) % SYM 14 %
DROPCUP,F=RORF(G,D,H,I,J) % SYM 15 %
M=INP(COINDROP) % SYM 16 %
K=NOT(F) % SYM 17 %
P=AND(K,E,L) % SYM 18 %
L=NOT(N) % SYM 19 %
EQUATIONS:
G = (K & L & M);
H = (F & E);
O = (P # Q);
END$

AppliconBRAVO netlist format

AppliconBRAVO netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.
Example
*** Desig 14DIP300
U1
*** Desig 14DIP300
U2
** NET GND
U1 7
U2 7
*** NET VCC
U1 14
U2 14
*** NET CLOCK
U1 10
*** NET Q
U1 6
U2 2
U1 9
*** NET OUT
U2 3
** NET B
U1 4
*** NET N00019
U1 3
U2 1
*** NET N00013
U1 5
U1 8
*** NET A
U1 1
U1 2

AppliconLEAP netlist format

AppliconLEAP netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.
    See the AppliconLEAP netlist format example for more information.
Example
*** NET GND
U1 7 14DIP300
U2 7 14DIP300
*** NET VCC
U1 14 14DIP300
U2 14 14DIP300
*** NET CLOCK
U1 10 14DIP300
*** NET Q
U1 6 14DIP300
U2 2 14DIP300
U1 9 14DIP300
*** NET OUT
U2 3 14DIP300
*** NET B
U1 4 14DIP300
*** NET N00019
U1 3 14DIP300
U2 1 14DIP300
** NET N00013
1 5 14DIP300
1 8 14DIP300
*** NET A
U1 1 14DIP300
U1 2 14DIP300

Cadnetix netlist format

Cadnetix netlists have the following characteristics:

  • Part names can contain up to 17 characters.
  • Module names can contain up to 15 characters.
  • Reference strings plus pin numbers can contain up to 12 characters.
  • Node names can contain up to 16 characters.
  • Pin numbers can contain up to three digits.
  • Pin names are not used.
  • Node numbers are not checked for length.
  • All ASCII characters are legal.
Example
PARTS LIST
74LS00 14DIP300 U1
74LS32 14DIP300 U2
EOS
NET LIST
NODENAME GND $
U1 7 U2 7
NODENAME VCC $
U1 14 U2 14
NODENAME CLOCK $
U1 10
NODENAME Q $
U1 6 U2 2 U1 9
NODENAME OUT $
U2 3
NODENAME B $
U1 4
NODENAME N00019 $
U1 3 U2 1
NODENAME N00013 $
U1 5 U1 8
NODENAME A $
U1 1 U1 2
EOS

Calay90 netlist format

The Calay 90 format creates two files: the netlist file and a component file. You must enter the component filename in the appropriate text box in the Create Netlist dialog box. Calay 90 netlists have the following characteristics:

  • Part names, module names, and reference strings can each contain up to 19 characters.
  • Node names can contain up to eight characters. Legal characters for node names are:
    + - 0..9 A..Z a..z
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • Pin numbers are not checked for length.
  • All ASCII characters are legal except as noted for node names.
Example
GND U1('7) U2('7);
VCC U1('14) U2('14);
CLOCK U1('10);
Q U1('6) U2('2) U1('9);
OUT U2('3);
B U1('4);
N00019 U1('3) U2('1);
N00013 U1('5) U1('8);
A U1('1) U1('2);

Calay netlist format

This is the older of two Calay netlists formats. The newer Calay format is Calay 90.
Calay netlists have the following characteristics:

  • Part names, module names, and reference strings can each contain up to 19 characters.
  • Node names can contain up to eight characters. Legal characters for node names are:
    + - 0..9 A..Z a..z
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • Pin numbers are not checked for length.
  • All ASCII characters are legal except as noted for node names.
Example

Calay netlists normally have a .NET file extension.

/GND U1(7) U2(7);
/VCC U1(14) U2(14);
/CLOCK U1(10);
/Q U1(6) U2(2) U1(9);
/OUT U2(3);
/B U1(4);
/N00019 U1(3) U2(1);
/N00013 U1(5) U1(8);
/A U1(1) U1(2);

Case netlist format

Sophia Systems & Technologies CASE netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal except as noted for node names.
Example
ASSERTIONS=OFF;VERSION=400;LOCATION=LOC;
[SIZE=1;TIMES=1;LOC=(U1);PLOC=U1;SHAPE=14DIP300]
1=A;
2=A;
3=N00019;
4=B;
5=N00013;
6=Q;
7=GND;
8=N00013;
9=Q;
10=CLOCK;
11=NC;
12=NC;
13=NC;
14=VCC;
;
[SIZE=1;TIMES=1;LOC=(U2);PLOC=U2;SHAPE=14DIP300]
1=N00019;
2=Q;
3=OUT;
4=NC;
5=NC;
6=NC;
7=GND;
8=NC;
9=NC;
10=NC;
11=NC;
12=NC;
13=NC;
14=VCC;
;
;

CBDS netlist format

BNR CBDS netlists have the following characteristics:

  • Part names, module names, reference strings, and pin numbers are not checked for length.
  • Node names can contain up to 20 characters. These characters are legal:
    / - 0..9 a..z A..Z
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal except as noted for node names.
Example
.SEARCH P,C
.DD U1 14DIP300
.DD U2 14DIP300
.S,GND,U1,7,U2,7
.S,VCC,U1,14,U2,14
.S,CLOCK,U1,10
.S,Q,U1,6,U2,2,U1,9
.S,OUT,U2,3
.S,B,U1,4
.S,N00019,U1,3,U2,1
.S,N00013,U1,5,U1,8
.S,A,U1,1,U1,2

Computervision netlist format

ComputerVision CADDS3 and CADDS4X netlists have the following characteristics:

  • Part names, module names, reference strings, and pin numbers are not checked for length.
  • Node names can contain up to 19 characters.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal except as noted for node names.
Example
0001 GND U1-7 U2-7
0002 VCC U1-14 U2-14
0003 CLOCK U1-10
0004 Q U1-6 U2-2 U1-9
0005 OUT U2-3
0006 B U1-4
0007 N00019 U1-3 U2-1
0008 N00013 U1-5 U1-8
0009 A U1-1 U1-2

DUMP netlist format

This format produces a flat netlist containing all the information on the schematic pages. No information is omitted or changed. You can use this netlist format when troubleshooting a design.

EDIF 2 0 0 netlist format

EEDesigner netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers are limited to five digits following the "N" prefix.
  • Legal characters are:
    0..9 a..z A..Z _(underscore)
    Case is not significant. When Capture encounters an illegal character, it issues a warning and makes the following changes:
    • Changes "-" to "MINUS"
    • Changes "+" to "PLUS"
    • Changes "\" and "/" to "BAR"
    • Changes all other illegal characters to "_"
EDIF 2 0 0 formats

Capture provides two EDIF netlist formats. The first format produces either hierarchical or flat netlist output, depending on your design structure and the active mode. It is accessible from the EDIF 2 0 0 tab in the Create Netlist dialog box. The second format produces only flat netlists, and is accessible through the Other tab in the Create Netlist dialog box.
Use the EDIF 2 0 0 tab if:

  • You want to include net, pin, or part properties in the netlist.
  • You want a hierarchical netlist.
    Use the Other tab if:
  • You want a flat netlist for a simple hierarchical design.
Hierarchical designs in EDIF

Capture manages the hierarchy by defining pages in the schematic folder as CELLs in the main LIBRARY. These cells can then be referred to by INSTANCE where needed. Because EDIF requires a define-before-use philosophy, the hierarchy appears to be inverted in the netlist (the root schematic page is the last CELL in the main LIBRARY).

Note: Some of the options specific to the EDIF netlist format are included to support PC Board Layout Tools 386+. If you are creating a netlist for use with PCB 386+, be sure to select the Allow non-EDIF characters option.

Example flat netlist
(edif (rename &FIG_BMINUS01 "FIG_B-01")
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 0 0 0 0 0 0)
(program "EDIF.DLL")
(comment "Original data from OrCAD CAPTURE schematic"))
(comment "Generic Netlist Example")
(comment "Thursday, November 12, 1998")
(comment "OrCAD-01")
(comment "A")
(comment "OrCAD")
(comment "9300 S.W. Nimbus Ave.")
(comment "Beaverton, OR 97008")
(comment "(503) 671-9500 Corporate Offices")
(comment "(503) 671-9400 Technical Support"))
(external OrCAD_LIB
(edifLevel 0)
(technology
(numberDefinition
(scale 1 1 (unit distance))))
(cell &74LS00
(cellType generic)
(comment "From OrCAD library D:\ORCAD DEMO\CAPTURE\SDT\FIG_B-01.OLB")
(view NetlistView
(viewType netlist)
(interface
(port &1 (direction INPUT))
(port &2 (direction INPUT))
(port &3 (direction OUTPUT))
(port &4 (direction INPUT))
(port &5 (direction INPUT))
(port &6 (direction OUTPUT))
(port &7 (direction INPUT))
(port &8 (direction OUTPUT))
(port &9 (direction INPUT))
(port &10 (direction INPUT))
(port &11 (direction OUTPUT))
(port &12 (direction INPUT))
(port &13 (direction INPUT))
(port &14 (direction INPUT)))))
(cell &74LS32
(cellType generic)
(comment "From OrCAD library D:\ORCAD DEMO\CAPTURE\SDT\FIG_B-01.OLB")
(view NetlistView
(viewType netlist)
(interface
(port &1 (direction INPUT))
(port &2 (direction INPUT))
(port &3 (direction OUTPUT))
(port &4 (direction INPUT))
(port &5 (direction INPUT))
(port &6 (direction OUTPUT))
(port &7 (direction INPUT))
(port &8 (direction OUTPUT))
(port &9 (direction INPUT))
(port &10 (direction INPUT))
(port &11 (direction OUTPUT))
(port &12 (direction INPUT))
(port &13 (direction INPUT))
(port &14 (direction INPUT))))))
(library MAIN_LIB
(edifLevel 0)
(technology
(numberDefinition
(scale 1 1 (unit distance))))
(cell (rename &FIG_BMINUS01 "FIG_B-01")
(cellType generic)
(view NetlistView
(viewType netlist)
(interface
(port &CLOCK (direction INPUT))
(port &OUT (direction OUTPUT))
(port &B (direction INPUT))
(port &A (direction INPUT)))
(contents
(instance &U1
(viewRef NetlistView
(cellRef &74LS00
(libraryRef OrCAD_LIB)))
(property PartValue (string "74LS00"))
(property ModuleValue (string "14DIP300"))
(property TimeStampValue (string "6CB84CBA")))
(instance &U2
(viewRef NetlistView
(cellRef &74LS32
(libraryRef OrCAD_LIB)))
(property PartValue (string "74LS32"))
(property ModuleValue (string "14DIP300"))
(property TimeStampValue (string "6E46169D")))
(net &GND
(joined
(portRef &7 (instanceRef &U1))
(portRef &7 (instanceRef &U2))))
(net &VCC
(joined
(portRef &14 (instanceRef &U1))
(portRef &14 (instanceRef &U2))))
(net &CLOCK
(joined
(portRef &CLOCK)
(portRef &10 (instanceRef &U1))))
(net &Q
(joined
(portRef &6 (instanceRef &U1))
(portRef &2 (instanceRef &U2))
(portRef &9 (instanceRef &U1))))
(net &OUT
(joined
(portRef &OUT)
(portRef &3 (instanceRef &U2))))
(net &B
(joined
(portRef &B)
(portRef &4 (instanceRef &U1))))
(net &N00019
(joined
(portRef &3 (instanceRef &U1))
(portRef &1 (instanceRef &U2))))
(net &N00013
(joined
(portRef &5 (instanceRef &U1))
(portRef &8 (instanceRef &U1))))
(net &A
(joined
(portRef &A)
(portRef &1 (instanceRef &U1))
(portRef &2 (instanceRef &U1))))))))
(design (rename &FIG_BMINUS01 "FIG_B-01")
(cellRef &FIG_BMINUS01
(libraryRef MAIN_LIB))))
Example hierarchical netlist
(edif FULLADD
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 1998 11 13 23 03 20)
(program "CAPTURE.EXE" (Version "9.00.1120"))
(comment "Original data from OrCAD/CAPTURE schematic"))
(comment "Hierarchy (Complex) Example")
(comment "Thursday, November 12, 1998")
(comment "OrCAD-06")
(comment "A")
(comment "OrCAD")
(comment "9300 S.W. Nimbus Ave.")
(comment "Beaverton, OR 97008")
(comment "(503)671-9500 Corporate Offices")
(comment "(503) 671-9400 Technical Support"))
(external OrCAD_LIB
(edifLevel 0)
(technology
(numberDefinition
(scale 1 1 (unit distance))))
(cell &74LS32
(cellType generic)
(comment "From OrCAD library FULLADD.OLB")
(view NetlistView
(viewType netlist)
(interface
(port &1 (direction INPUT))
(port &2 (direction INPUT))
(port &3 (direction OUTPUT))
(port &14 (direction INPUT))
(port &7 (direction INPUT))
(port &4 (direction INPUT))
(port &5 (direction INPUT))
(port &6 (direction OUTPUT))
(port &9 (direction INPUT))
(port &10 (direction INPUT))
(port &8 (direction OUTPUT))
(port &12 (direction INPUT))
(port &13 (direction INPUT))
(port &11 (direction OUTPUT)))))
(cell &74LS08
(cellType generic)
(comment "From OrCAD library FULLADD.OLB")
(view NetlistView
(viewType netlist)
(interface
(port &1 (direction INPUT))
(port &2 (direction INPUT))
(port &3 (direction OUTPUT))
(port &14 (direction INPUT))
(port &7 (direction INPUT))
(port &4 (direction INPUT))
(port &5 (direction INPUT))
(port &6 (direction OUTPUT))
(port &9 (direction INPUT))
(port &10 (direction INPUT))
(port &8 (direction OUTPUT))
(port &12 (direction INPUT))
(port &13 (direction INPUT))
(port &11 (direction OUTPUT)))))
(cell &74LS04
(cellType generic)
(comment "From OrCAD library FULLADD.OLB")
(view NetlistView
(viewType netlist)
(interface
(port &1 (direction INPUT))
(port &2 (direction OUTPUT))
(port &14 (direction INPUT))
(port &7 (direction INPUT))
(port &3 (direction INPUT))
(port &4 (direction OUTPUT))
(port &5 (direction INPUT))
(port &6 (direction OUTPUT))
(port &9 (direction INPUT))
(port &8 (direction OUTPUT))
(port &11 (direction INPUT))
(port &10 (direction OUTPUT))
(port &13 (direction INPUT))
(port &12 (direction OUTPUT))))))
(library MAIN_LIB
(edifLevel 0)
(technology
(numberDefinition
(scale 1 1 (unit distance))))
(cell EX6B
(cellType generic)
(view NetlistView
(viewType netlist)
(interface
(port X (direction INPUT))
(port Y (direction INPUT))
(port CARRY (direction OUTPUT))
(port SUM (direction OUTPUT)))
(contents
(instance U1
(viewRef NetlistView
(cellRef &74LS32
(libraryRef OrCAD_LIB))))
(instance U2
(viewRef NetlistView
(cellRef &74LS08
(libraryRef OrCAD_LIB))))
(instance U3
(viewRef NetlistView
(cellRef &74LS04
(libraryRef OrCAD_LIB))))
(net Y
(joined
(portRef &9 (instanceRef U2))
(portRef &3 (instanceRef U3))
(portRef &4 (instanceRef U2))
(portRef Y)))
(net CARRY
(joined
(portRef &8 (instanceRef U2))
(portRef CARRY)))
(net SUM
(joined
(portRef &6 (instanceRef U1))
(portRef SUM)))
(net X_BAR
(joined
(portRef &5 (instanceRef U2))
(portRef &2 (instanceRef U3))))
(net X
(joined
(portRef &10 (instanceRef U2))
(portRef &1 (instanceRef U3))
(portRef &1 (instanceRef U2))
(portRef X)))
(net N00037
(joined
(portRef &5 (instanceRef U1))
(portRef &6 (instanceRef U2))))
(net N00035
(joined
(portRef &3 (instanceRef U2))
(portRef &4 (instanceRef U1))))
(net GND
(joined
(portRef &7 (instanceRef U3))
(portRef &7 (instanceRef U2))
(portRef &7 (instanceRef U1))))
(net VCC
(joined
(portRef &14 (instanceRef U3))
(portRef &14 (instanceRef U2))
(portRef &14 (instanceRef U1))))
(net N5056796111
(joined
(portRef &4 (instanceRef U3))
(portRef &2 (instanceRef U2)))))))
(cell FULLADD
(cellType generic)
(view NetlistView
(viewType netlist)
(interface
(port SUM (direction OUTPUT))
(port X (direction INPUT))
(port Y (direction INPUT))
(port CARRY_OUT (direction OUTPUT))
(port CARRY_IN (direction INPUT)))
(contents
(instance U1
(viewRef NetlistView
(cellRef &74LS32
(libraryRef OrCAD_LIB))))
(instance halfadd_A
(viewRef NetlistView
(cellRef EX6B)))
(instance halfadd_B
(viewRef NetlistView
(cellRef EX6B)))
(net CARRY_IN
(joined
(portRef X (instanceRef halfadd_A))
(portRef CARRY_IN)))
(net SUM
(joined
(portRef SUM (instanceRef halfadd_A))
(portRef SUM)))
(net N00015
(joined
(portRef CARRY (instanceRef halfadd_A))
(portRef &1 (instanceRef U1))))
(net X
(joined
(portRef X (instanceRef halfadd_B))
(portRef X)))
(net N00013
(joined
(portRef Y (instanceRef halfadd_A))
(portRef SUM (instanceRef halfadd_B))))
(net Y
(joined
(portRef Y (instanceRef halfadd_B))
(portRef Y)))
(net N00025
(joined
(portRef CARRY (instanceRef halfadd_B))
(portRef &2 (instanceRef U1))))
(net CARRY_OUT
(joined
(portRef &3 (instanceRef U1))
(portRef CARRY_OUT)))
(net VCC
(joined
(portRef &14 (instanceRef U1))))
(net GND
(joined
(portRef &7 (instanceRef U1))))))))
(design FULLADD
(cellRef FULLADD
(libraryRef MAIN_LIB))))

EEDesigner netlist format

EEDesigner netlists have the following characteristics:

  • Part names, module names, and pin numbers are not checked for length.
  • Reference strings are limited to eight characters.
  • Node names are not supported.
  • Node numbers are limited to three digits following the "UN" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.
Example
(PATH,OrCAD()
(COMPONENTS
U1 ,14DIP300
U2 ,14DIP300
)
(NODES
(UN001
U1 , 7
U2 , 7
)
(UN002
U1 , 14
U2 , 14
)
(UN003
U1 , 10
)
(UN004
U1 , 6
U2 , 2
U1 , 9
)
(UN005
U2 , 3
)
(UN006
U1 , 4
)
(UN007
U1 , 3
U2 , 1
)
(UN008
U1 , 5
U1 , 8
)
(UN009
U1 , 1
U1 , 2
)
)
),OrCAD

Futurenet netlist format

FutureNet netlists have the following characteristics:

  • Part names are limited to 16 characters.
  • Module names, node names, and pin numbers are not checked for length.
  • Reference strings are limited to six characters.
  • Node numbers are limited to eight digits.
    You can use Capture to generate FutureNet pinlists or netlists.
Pinlist example
PINLIST,2
(DRAWING,ORCAD.PIN,1-1
(SYM,1
DATA,2,U1
DATA,3,74LS00
DATA,4,14DIP300
PIN,,A,1-1,5,23,I0_A
PIN,,A,1-1,5,23,I1_A
PIN,,N00019,1-1,5,21,O_A
PIN,,B,1-1,5,23,I0_B
PIN,,N00013,1-1,5,23,I1_B
PIN,,Q,1-1,5,21,O_B
PIN,,GND,1-1,5,23,GND
PIN,,N00013,1-1,5,21,O_C
PIN,,Q,1-1,5,23,I0_C
PIN,,CLOCK,1-1,5,23,I1_C
PIN,,UN000001,1-1,5,21,O_D
PIN,,UN000002,1-1,5,23,I0_D
PIN,,UN000003,1-1,5,23,I1_D
PIN,,VCC,1-1,5,23,VCC
)
(SYM,2
DATA,2,U2
DATA,3,74LS32
DATA,4,14DIP300
PIN,,N00019,1-1,5,23,I0_A
PIN,,Q,1-1,5,23,I1_A
PIN,,OUT,1-1,5,21,O_A
PIN,,UN000004,1-1,5,23,I0_B
PIN,,UN000005,1-1,5,23,I1_B
PIN,,UN000006,1-1,5,21,O_B
PIN,,GND,1-1,5,23,GND
PIN,,UN000007,1-1,5,21,O_C
PIN,,UN000008,1-1,5,23,I0_C
PIN,,UN000009,1-1,5,23,I1_C
PIN,,UN000010,1-1,5,21,O_D
PIN,,UN000011,1-1,5,23,I0_D
PIN,,UN000012,1-1,5,23,I1_D
PIN,,VCC,1-1,5,23,VCC
)
SIG,GND,1-1,5,GND
SIG,VCC,1-1,5,VCC
SIG,CLOCK,1-1,5,CLOCK
SIG,Q,1-1,5,Q
SIG,OUT,1-1,5,OUT
SIG,B,1-1,5,B
SIG,N00019,1-1,5,N00019
SIG,N00013,1-1,5,N00013
SIG,A,1-1,5,A
)
Netlist example
NETLIST,2
(DRAWING,ORCAD.NET,1-1
DATA,50,Generic Netlist Example
DATA,51,OrCAD-01
DATA,52,A
DATA,54,Thursday, November 12, 1998
)
(SYM,1-1,1
DATA,2,U1
DATA,3,74LS00
DATA,4,14DIP300
DATA,23,I0_A
DATA,23,I1_A
DATA,21,O_A
DATA,23,I0_B
DATA,23,I1_B
DATA,21,O_B
DATA,23,GND
DATA,21,O_C
DATA,23,I0_C
DATA,23,I1_C
DATA,21,O_D
DATA,23,I0_D
DATA,23,I1_D
DATA,23,VCC
)
(SYM,1-1,2
DATA,2,U2
DATA,3,74LS32
DATA,4,14DIP300
DATA,23,I0_A
DATA,23,I1_A
DATA,21,O_A
DATA,23,I0_B
DATA,23,I1_B
DATA,21,O_B
DATA,23,GND
DATA,21,O_C
DATA,23,I0_C
DATA,23,I1_C
DATA,21,O_D
DATA,23,I0_D
DATA,23,I1_D
DATA,23,VCC
)
(SIG,,GND,1-1,5,GND
PIN,1-1,1,U1,23,GND
PIN,1-1,2,U2,23,GND
)
(SIG,,VCC,1-1,5,VCC
PIN,1-1,1,U1,23,VCC
PIN,1-1,2,U2,23,VCC
)
(SIG,,CLOCK,1-1,5,CLOCK
PIN,1-1,1,U1,23,I1_C
)
(SIG,,Q,1-1,5,Q
PIN,1-1,1,U1,21,O_B
PIN,1-1,2,U2,23,I1_A
PIN,1-1,1,U1,23,I0_C
)
(SIG,,OUT,1-1,5,OUT
PIN,1-1,2,U2,21,O_A
)
(SIG,,B,1-1,5,B
PIN,1-1,1,U1,23,I0_B
)
(SIG,,N00019,1-1,5,N00019
PIN,1-1,1,U1,21,O_A
PIN,1-1,2,U2,23,I0_A
)
(SIG,,N00013,1-1,5,N00013
PIN,1-1,1,U1,23,I1_B
PIN,1-1,1,U1,21,O_C
)
(SIG,,A,1-1,5,A
PIN,1-1,1,U1,23,I0_A
PIN,1-1,1,U1,23,I1_A
)

HiLo netlist format

HiLo netlists have the following characteristics:

  • Part names, module names, reference strings, and pin numbers are not checked for length.
  • Node names are limited to 14 characters.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.
Example
** Generic Netlist Example Revised: Thursday, November 12, 1998
** OrCAD-01 Revision: A
** OrCAD
** 9300 S.W. Nimbus Ave.
** Beaverton, OR 97008
** (503) 671-9500 Corporate Offices
** (503) 671-9400 Technical Support
CCT ORCAD (
** Please put your circuit interface definition here
);
14DIP300
U1 (
A,
A,
N00019,
B,
N00013,
Q,
GND,
N00013,
Q,
CLOCK,
,
,
,
VCC
);
14DIP300
U2 (
N00019,
Q,
OUT,
,
,
,
GND,
,
,
,
,
,
,
VCC
);

Intel ADF netlist format

Intel ADF netlists have the following characteristics:

  • Part names, module names, reference strings, and pin numbers are not checked for length.
  • Node numbers are not used.
  • All ASCII characters are legal.
Intel ADF netlist constraints

When you create an Intel ADF netlist, you must include the OrCAD-supplied ALTERA_P.OLB and ALTERA_M.OLB libraries in your project. You can use only the parts in these two libraries to create the schematic folder.
Inputs and outputs are handled differently in Capture than in the Altera software. Capture defines inputs and outputs with hierarchical ports and library objects. Altera defines inputs and outputs with a library object, which is then tagged with the appropriate pin number. In the example schematic page, the CLOCK signal is an input and the STROBE signal is an output.
Also, library objects with unused pins default to predefined levels in the Altera software. Because Capture does not default unconnected pins to any particular level, you must tie all unused pins to the appropriate level.

Intel ADF pipe commands

You can place equations in your schematic folder to be included in the netlist. To place these equations on the schematic page, choose the Text command from the Place menu.
Each equation must start with the pipe character (|). The first line must be:

|EQUATIONS

This tells Capture that some Intel ADF equations need to be included in the netlist. The equations can contain any information you want to include in the netlist.

Intel ADF title block information

Title block information is placed in the first 10 lines of the netlist. The following table shows an example netlist header and the title block information from which the header was extracted. Header information in bold is text entered in the schematic page's title block

.

Line

Example header

Title block field

1

ADF Example

Title of schematic page

1

May 15, 2002

Date

2

OrCAD-03

Document number

2

D

Revision Code

3

Dade’s House of Boards

Organization Name

4

933 SW 52nd St.

1st Address Line

6

Turbo=ON

3rd Address Line

7

5C031

4th Address Line

WireList netlist format

WireList netlists have the following characteristics:

  • Part and node names are not checked for length.
  • Module names are limited to twenty-nine characters.
  • Reference strings are limited to nine characters.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin numbers are limited to seven characters.
  • Pin names are limited to fifteen characters.
  • Legal characters for node numbers are 0..9.
  • Legal characters for pin numbers are 0..9, unless the option Do not output pin numbers for Grid Array parts is selected. If you select this option, Capture skips nonnumeric pin numbers, such as those on grid array parts, and any ASCII character is legal.
  • All ASCII characters are legal except as noted for node numbers and pin numbers.

Note: WireList netlists generated by Capture use all uppercase letters for pin names, pin numbers, and net names.

For more information, see the WireList netlist example.

Example

WireList netlists normally have an .NET file extension.

Wire List
Generic Netlist Example Revised: Thursday, November 12, 1998
OrCAD-01 Revision: A
OrCAD
9300 S.W. Nimbus Ave.
Beaverton, OR 97008
(503) 671-9500 Corporate Offices
(503) 671-9400 Technical Support
<<< Component List >>>
74LS00 U1 14DIP300
74LS32 U2 14DIP300
<<< Wire List >>>
 NODE REFERENCE PIN # PIN NAME PIN TYPE PART VALUE
[00001] GND
 U1 7 GND Power 74LS00
 U2 7 GND Power 74LS32
[00002] VCC
 U1 14 VCC Power 74LS00
 U2 14 VCC Power 74LS32
[00003] CLOCK
 U1 10 I1_C Input 74LS00
[00004] Q
 U1 6 O_B Output 74LS00
 U2 2 I1_A Input 74LS32
 U1 9 I0_C Input 74LS00
[00005] OUT
 U2 3 O_A Output 74LS32
[00006] B
 U1 4 I0_B Input 74LS00
[00007] N00019
 U1 3 O_A Output 74LS00
 U2 1 I0_A Input 74LS32
[00008] N00013
 U1 5 I1_B Input 74LS00
 U1 8 O_C Output 74LS00
[00009] A
 U1 1 I0_A Input 74LS00
 U1 2 I1_A Input 74LS00
Example
ADF Example Revised: Friday, November 13, 1998
OrCAD-02 Revision: A
OrCAD
9300 S.W. Nimbus Ave.
TURBO = ON
5C031
OPTIONS:TURBO = ON
PART:5C031
INPUTS:
CLOCK
ENABLE
COINDROP
CUPFULL
RESET
OUTPUTS:
STROBE
POURDRNK
DROPCUP
NETWORK:
J=INP(ENABLE) % SYM 1 %
N=INP(CUPFULL) % SYM 2 %
O=OR(P,Q) % SYM 3 %
POURDRNK,E=RORF(O,D,H,I,J) % SYM 4 %
Q=AND(F,R) % SYM 5 %
R=NOT(E) % SYM 6 %
B=XOR(E,F) % SYM 7 %
A=AND(B,C) % SYM 8 %
STROBE=CONF(A,VCC) % SYM 9 %
C=NOT(D) % SYM 10 %
D=INP(CLOCK) % SYM 11 %
H=AND(F,E) % SYM 12 %
I=INP(RESET) % SYM 13 %
G=AND(K,L,M) % SYM 14 %
DROPCUP,F=RORF(G,D,H,I,J) % SYM 15 %
M=INP(COINDROP) % SYM 16 %
K=NOT(F) % SYM 17 %
P=AND(K,E,L) % SYM 18 %
L=NOT(N) % SYM 19 %
EQUATIONS:
G = (K & L & M);
H = (F & E);
O = (P # Q);
END$

Intergraph netlist format

Intel ADF netlists have the following characteristics:

  • Part names, module names, reference strings, and pin numbers are not checked for length.
  • Node numbers can have up to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.
Example
%PART
14DIP300 U1
14DIP300 U2
%NET
GND U1-7 U2-7
VCC U1-14 U2-14
CLOCK U1-10
Q U1-6 U2-2 U1
OUT U2-3
B U1-4
N00019 U1-3 U2-1
N00013 U1-5 U1-8
A U1-1 U1-2
$

Mentor netlist format

Mentor Graphics BoardStation Version 7 netlists have the following characteristics:

  • Part names, module names, and reference strings are limited to nineteen characters.
  • Node names and pin numbers are not checked for length.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.

Note: Capture includes a netlister (available from the Accessories menu) developed specifically for Mentor netlist generation. There is also a document that discusses the use of the netlister. It is available in the Vendor directory of your Capture installation.

Example component file
# OrCAD X Formatted Netlist for MENTOR Board Station V6
# Reference Value Field Module Field
U1 PART 74LS00 14DIP300
U2 PART 74LS32 14DIP300
Example netlist
NET 'GND' U1-7 U2-7
NET 'VCC' U1-14 U2-14
NET 'CLOCK' U1-10
NET 'Q' U1-6 U2-2 U1-9
NET 'OUT' U2-3
NET 'B' U1-4
NET 'N00019' U1-3 U2-1
NET 'N00013' U1-5 U1-8
NET 'A' U1-1 U1-2

Multiwire netlist format

MultiWire netlists have the following characteristics:

  • Part names and module names are not checked for length.
  • Reference strings and pin numbers together are limited to thirty-two characters.
  • Node names are limited to sixteen characters.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.
Example
GND U1 7
GND U2 7
VCC U1 14
VCC U2 14
CLOCK U1 10
Q U1 6
Q U2 2
Q U1 9
OUT U2 3
B U1 4
N00019 U1 3
N00019 U2 1
N00013 U1 5
N00013 U1 8
A U1 1
A U1 2
-1

OHDL netlist format

OrCAD PLD 386+ netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.
    For more information, see the OrCAD web site.
OHDL netlist constraints

The OHDL netlist format uses the OrCAD-supplied PLDGATES.OLB and TTL.OLB libraries. Be sure you include one of these libraries in your project.

Example

OHDL netlists normally have a .PLD file extension.

|| CNTMUX (Example for MACH 110) Revised: Friday, November 13, 1998
|| D:\ORCAD DEMO\CAPTURE\NETLIST UPDATES\DESIGN6\Revision: ?
|| OrCAD
||
||
||
||
||
| Type: "IFX780_132"
|
|
| Netlist:
| {
| PAD (I0,"IN") | PAD1
| PAD (I6,"IN") | PAD10
| PAD (O3,"OUT") | PAD11
| PAD (I7,"IN") | PAD12
| PAD (O4,"OUT") | PAD13
| PAD (I8,"IN") | PAD14
| PAD (O5,"OUT") | PAD15
| PAD (I9,"IN") | PAD16
| PAD (O6,"OUT") | PAD17
| PAD (I10,"IN") | PAD18
| PAD (O7,"OUT") | PAD19
| PAD (I1,"IN") | PAD2
| PAD (I11,"IN") | PAD20
| PAD (O8,"OUT") | PAD21
| PAD (I12,"IN") | PAD22
| PAD (O9,"OUT") | PAD23
| PAD (O10,"OUT") | PAD24
| PAD (I14,"IN") | PAD25
| PAD (O11,"OUT") | PAD26
| PAD (I15,"IN") | PAD27
| PAD (O12,"OUT") | PAD28
| PAD (O13,"OUT") | PAD29
| PAD (I2,"IN") | PAD3
| PAD (LOAD,"IN") | PAD30
| PAD (O14,"OUT") | PAD31
| PAD (O15,"OUT") | PAD32
| PAD (CLK,"IN") | PAD33
| PAD (UP,"IN") | PAD34
| PAD (COUNT,"IN") | PAD35
| PAD (SELECT,"IN") | PAD36
| PAD (I3,"IN") | PAD4
| PAD (O0,"OUT") | PAD5
| PAD (I4,"IN") | PAD6
| PAD (O1,"OUT") | PAD7
| PAD (I5,"IN") | PAD8
| PAD (O2,"OUT") | PAD9
| G169 (UP,CLK,I0,I1,I2,I3,GND,-,N00185,N00193,Q3,Q2,Q1,Q0,N00177) | U1
| G257 (SELECT,Q12,I12,O12,Q13,I13,O13,-,O14,I14,Q14,O15,I15,Q15,GND) | U10
| G257 (SELECT,Q0,I0,O0,Q1,I1,O1,-,O2,I2,Q2,O3,I3,Q3,GND) | U2
| G169 (UP,CLK,I4,I5,I6,I7,GND,-,N00185,N00177,Q7,Q6,Q5,Q4,-) | U3
| G04 (LOAD,N00185) | U4
| G257 (SELECT,Q4,I4,O4,Q5,I5,O5,-,O6,I6,Q6,O7,I7,Q7,GND) | U5
| G169 (UP,CLK,I8,I9,I10,I11,GND,-,N00185,N00193,Q11,Q10,Q9,Q8,N00355) | U6
| G04 (COUNT,N00193) | U7
| G257 (SELECT,Q8,I8,O8,Q9,I9,O9,-,O10,I10,Q10,O11,I11,Q11,GND) | U8
| G169 (UP,CLK,I12,I13,I14,I15,GND,-,N00185,N00355,Q15,Q14,Q13,Q12,-) | U9
| }
|
|Vectors:
|{ Display COUNT, LOAD, SELECT, CLK, \
| (I[15..8])d, (O[15..8])d, \
| (I[7..0])d, (O[7..0])d
|
| Test LOAD=1; CLK
| Test LOAD=0; COUNT=1; UP=1; CLK=25(0,1)
| Set I[15..8] = 10
| Set I[7..0] = 11
| Test SELECT=1,0
| Test LOAD=0; COUNT=1; UP=0; CLK=25(0,1)
| Test SELECT=1,0
| End }

PADS 2000 netlist format

PADS 2000 netlists have the following characteristics:

  • Part names, module names, and pin numbers are not checked for length.
  • Reference strings are limited to sixteen characters.
  • Header information is included at the top of the netlist file:
!PADS-POWERPCB-V2
  • Net and signal names are limited to forty-seven characters.
  • Legal characters for reference strings and node names are limited to:
    • ~ ! # $ % _ - =
    • + | / . : ; < >
    • A..Z a..z 0..9
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal except as noted for reference strings and node names.

Note: You can add a property called "tracewidth" to nets in Capture. The value of tracewidth will carry through into the PADS 2000 netlist. Capitalization of this property is important, and the property won't appear in the netlist if any uppercase letters are used in the property name.

For more information see the PADS website.

Example

This netlist was created with no options selected. PADS 2000 netlists normally have a .ASC file extension.
The header information in this example was created without the Create Pads BGA netlist option selected. If you choose this option when you create the PADS netlist, the header information will appear differently. In effect, choosing the Create Pads BGA netlist option causes Capture to generate a Powerpcb v3.0 netlist.

*PADS 2000*
*PART*
U1 14DIP300
U2 14DIP300
*NET*
*SIGNAL* GND
U1.7 U2.7
*SIGNAL* VCC
U1.14 U2.14
*SIGNAL* CLOCK
U1.10
*SIGNAL* Q
U1.6 U2.2 U1.9
*SIGNAL* OUT
U2.3
*SIGNAL* B
U1.4
*SIGNAL* N00019
U1.3 U2.1
*SIGNAL* N00013
U1.5 U1.8
*SIGNAL* A
U1.1 U1.2
*END*

PADS PCB netlist format

PADS-Software PADS PowerPCB netlists have the following characteristics:

  • Part names, module names, and pin numbers are not checked for length.
  • Reference strings are limited to sixteen characters.
  • Header information is included at the top of the netlist file:
!PADS-POWERPCB-V2
  • Net and signal names are limited to twelve characters.
  • Legal characters for reference strings and node names are limited to:
    • ~ ! # $ % _ - =
    • + | / . : ; < >
    • A..Z a..z 0..9
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal except as noted for reference strings and node names.
Example

This netlist was created with no options selected. PADS-PCB netlists normally have a .ASC file extension.
The header information in this example was created without the Create Pads BGA netlist option selected. If you choose this option when you create the PADS netlist, the header information will appear differently. In effect, choosing the Create Pads BGA netlist option causes Capture to generate a Powerpcb v3.0 netlist.

*PADS-PCB*
*PART*
U1 14DIP300
U2 14DIP300
*NET*
*SIGNAL* GND
U1.7 U2.7
*SIGNAL* VCC
U1.14 U2.14
*SIGNAL* CLOCK
U1.10
*SIGNAL* Q
U1.6 U2.2 U1.9
*SIGNAL* OUT
U2.3
*SIGNAL* B
U1.4
*SIGNAL* N00019
U1.3 U2.1
*SIGNAL* N00013
U1.5 U1.8
*SIGNAL* A
U1.1 U1.2
*END*

PCAD netlist format

PCAD PCB netlists from ACCEL Technologies have the following characteristics:

  • Part names, module names, reference strings, and pin numbers are not checked for length.
  • Node names are limited to eight characters.
  • Node numbers are limited to five digits following the "NET" prefix.
  • Pin names are not used.
  • Characters are not checked for legality.
    For more information, see the ACCEL Technologies web site, the Protel web site, and the netlist example.
Example

This netlist was created with no options selected. PCAD netlists normally have a .NET file extension.

{COMPONENT ORCAD.PCB
 {ENVIRONMENT LAYS.PCB}
 {PDIFvrev 1.30}
 {DETAIL
 {SUBCOMP
{I 14DIP300.PRT U1
{CN
 1 A
 2 A
 3 N00019
 4 B
 5 N00013
 6 Q
 7 GND
 8 N00013
 9 Q
 10 CLOCK
 11 ?
 12 ?
 13 ?
 14 VCC
}
}
{I 14DIP300.PRT U2
{CN
 1 N00019
 2 Q
 3 OUT
 4 ?
 5 ?
 6 ?
 7 GND
 8 ?
 9 ?
 10 ?
 11 ?
 12 ?
 13 ?
 14 VCC
}
}
}
}
}

PCADnlt netlist format

PCADnlt netlists from ACCEL Technologies have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Legal characters for node names are limited to:
$ - + _ (underscore)
A..Z a..z 0..9
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal except as noted for node names.
    For more information, see the ACCEL Technologies web site, the Protel web site.
Example

PCADnlt netlists normally have a .NET file extension.

% Generic Netlist Example Revised: Thursday, November 12, 1998
% OrCAD-01 Revision: A
% OrCAD
% 9300 S.W. Nimbus Ave.
% Beaverton, OR 97008
% (503) 671-9500 Corporate Offices
% (503) 671-9400 Technical Support
BOARD = ORCAD.PCB;
PARTS
14DIP300 = U1, % 74LS00
 U2; % 74LS32
NETS
GND = U1/7 U2/7 ;
VCC = U1/14 U2/14 ;
CLOCK = U1/10 ;
Q = U1/6 U2/2 U1/9 ;
OUT = U2/3 ;
B = U1/4 ;
N00019 = U1/3 U2/1 ;
N00013 = U1/5 U1/8 ;
A = U1/1 U1/2 ;

PCBII and PCBIIL netlist formats

PCB netlists are used with OrCAD's PCB II Layout Tools. See the PCB II User's Guide for details.
The PCBII and PCBIIL netlist formats are identical with the following exception: the PCBIIL.DLL netlist format has no restrictions on netname length.
PCB netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers are limited to five digits following the "N" prefix.
  • All ASCII characters are legal.
  • Footprint names are limited to eight characters.
  • PCBII (but not PCBIIL) net names are limited to eight characters.
    For more information, see the OrCAD web site.

PDUMP netlist format

This format produces a parts list containing all the information on the schematic pages. No information is omitted or changed. You can use this netlist format when troubleshooting a project.

PLD netlist format

This file produces netlists that define logic for use with Programmable Logic Design Tools 386+. See the Programmable Logic Design Tools User's Guide and the Programmable Logic Design Tools Reference Guide for details.
PLD netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Pin names are not used.
  • All ASCII characters are legal.
    For more information, see the OrCAD web site.
PLD netlist constraints

When you create a PLD netlist, be sure to include the OrCAD-supplied PLDGATES.OLB library in your project. You can use only the parts in PLDGATES.OLB, DEVICE.OLB (VCC, POWER, GND), and TTL.OLB (most 74LSxx) in a schematic folder to be netlisted for PLD.

Example

This netlist was created with no options selected. PLD netlists normally have a .NET file extension.

|| PLD Netlist Example Revised: Friday, November 13, 1998
|| OrCAD-05 Revision: A
|| OrCAD
|| 9300 S.W. Nimbus Ave.
|| Beaverton, OR 97008
|| (503) 671-9500 Corporate Offices
|| (503) 671-9400 Technical Support
||
| Netlist: A0,A1,B1,B0
| ->
| Y0,Y3,Y1,Y2
| {
| G08 (B0,A0,Y0) | U1
| G32 (N00103,N00107,N00095) | U10
| G04 (B1,N00113) | U11
| G11 (N00113,B0,-,-,-,-,-,-,-,-,-,N00107,A1) | U12
| G11 (B1,A1,-,-,-,-,-,-,-,-,-,N00133,N00137) | U13
| G04 (A0,N00137) | U14
| G32 (N00133,N00145,Y2) | U15
| G04 (B0,N00151) | U16
| G11 (B1,N00151,-,-,-,-,-,-,-,-,-,N00145,A1) | U17
| G21 (A0,A1,-,B0,B1,Y3) | U18
| G04 (A0,N00063) | U2
| G11 (N00063,B0,-,-,-,-,-,-,-,-,-,N00069,A1) | U3
| G32 (N00069,N00083,N00087) | U4
| G04 (A1,N00081) | U5
| G11 (B1,N00081,-,-,-,-,-,-,-,-,-,N00083,A0) | U6
| G32 (N00087,N00095,Y1) | U7
| G04 (B0,N00101) | U8
| G11 (B1,N00101,-,-,-,-,-,-,-,-,-,N00103,A0) | U9
| }

Protel2 netlist format

Protel2 netlists have the following characteristics:

  • Part names, module names, reference strings, and node names can be up to 16 characters in length.
  • Node numbers are limited to 5 digits (plus the leading 'N'.
  • Pin numbers are not checked for length.
  • The Reference and ModuleName must be in uppercase only.
  • All ASCII characters are legal except { '()[],-'}.
    For more information, see the Protel web site.
Example

Accel netlists normally have a .NET file extension.
This example was created with the combined property strings for Create Netlist set to their default values, as shown below:

]
[
DESIGNATOR
C10
FOOTPRINT
SM/C_0805
PARTTYPE
390PF
DESCRIPTION
]
[
DESIGNATOR
C100
FOOTPRINT
0.1UF
PARTTYPE
0.1UF
DESCRIPTION
]
[
DESIGNATOR
C101
FOOTPRINT
0.1UF
PARTTYPE
0.1UF
DESCRIPTION

RecalRedac netlist format

The newer version of the RacalRedac netlist format is RINF.
Zuken-Redac CADStar PCB netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.

    For more information, see the Zuken-Redac web site at http://www.zuken.com/.

Example

RacalRedac netlists normally have a .NET file extension.

.PCB
.REM Generic Netlist Example Revised: Thursday, November 12, 1998
.REM OrCAD-01 Revision: A
.REM OrCAD
.REM 9300 S.W. Nimbus Ave.
.REM Beaverton, OR 97008
.REM (503) 671-9500 Corporate Offices
.REM (503) 671-9400 Technical Support
.CON
.COD 2
.REM GND
U1 7 U2 7
.REM VCC
U1 14 U2 14
.REM CLOCK
U1 10
.REM Q
U1 6 U2 2 U1 9
.REM OUT
U2 3
.REM B
U1 4
.REM N00019
U1 3 U2 1
.REM N00013
U1 5 U1 8
.REM A
U1 1 U1 2
.EOD

RINF netlist format

Zuken-Redac Visual PCB netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.
Example

RINF netlists normally have a .NET file extension.

 .HEA
.APP "Cadstar RINF Output - Version 2.3"
.UNI INCH 1000.0 in
.TYP FULL
.JOB "FIG_B-01"
.ADD_COM U1 "14DIP300"
.ADD_COM U2 "14DIP300"
.ADD_TER U1 7 "GND"
.TER U2 7
.ADD_TER U1 14 "VCC"
.TER U2 14
.ADD_TER U1 10 "CLOCK"
.ADD_TER U1 6 "Q"
.TER U2 2
 U1 9
.ADD_TER U2 3 "OUT"
.ADD_TER U1 4 "B"
.ADD_TER U1 3 "N00019"
.TER U2 1
.ADD_TER U1 5 "N00013"
.TER U1 8
.ADD_TER U1 1 "A"
.TER U1 2
.END

Scicards netlist format

Harris EDA SciCards netlists have the following characteristics:

  • Part names are limited to seventeen characters.
  • Module names are limited to fifteen characters.
  • Reference strings and pin numbers combined are limited to twelve characters.
  • Pin numbers are limited to three characters.
  • Node names are limited to eight characters.
  • Node numbers are not checked for length.
  • Pin names are not used.
  • All ASCII characters are legal.
    For more information, see the netlist example.
Example

Scicards netlists normally have a .NET file extension.

PARTS LIST
74LS00 14DIP300 U1
74LS32 14DIP300 U2
EOS
NET LIST
NODENAME GND $
 U1 7 U2 7
NODENAME VCC $
 U1 14 U2 14
NODENAME CLOCK $
 U1 10
NODENAME Q $
 U1 6 U2 2 U1 9
NODENAME OUT $
 U2 3
NODENAME B $
 U1 4
NODENAME N00019 $
 U1 3 U2 1
NODENAME N00013 $
 U1 5 U1 8
NODENAME A $
 U1 1 U1 2
EOS

Tango netlist format


ACCEL Technologies Tango PCB and Tango PRO netlists have the following characteristics:

  • Part names, module names, reference strings, and node names are limited to sixteen characters.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin numbers are not checked for length.
  • Pin names are not used.
  • Reference strings and module names must be uppercase characters.
  • All ASCII characters are legal except:
( ) [ ] - (dash) , (comma)

and as noted for reference strings and module names.

Telesis netlist format

Cadence Telesis netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers are limited to five digits following the N prefix.
  • Pin names are not used.
  • All ASCII characters are legal.
The Telesis netlist created from Capture cannot be imported into PCB Editor. In the Create Netlist dialog box, use the PCB tab to generate a netlist that can be used in PCB Editor.

Example

Telesis netlists have a .NET file extension.

$PACKAGES
14DIP300! 74LS00; U1
14DIP300! 74LS32; U2
$NETS
GND; U1.7 U2.7
VCC; U1.14 U2.14
CLOCK; U1.10
Q; U1.6 U2.2 U1.9
OUT; U2.3
B; U1.4
N00019; U1.3 U2.1
N00013; U1.5 U1.8
A; U1.1 U1.2
$END

Vectron netlist format

Vectron netlists have the following characteristics:

  • Part names, module names, and pin numbers are not checked for length.
  • Reference strings are limited to eight characters.
  • Node names are limited to twelve characters.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin names are not used.
  • All ASCII characters are legal.
    In addition to the netlist file, Capture also creates a part list file when you select the Vectron netlist format. You must enter a second filename in the Destination 2 text box on the Netlist Format dialog box.
Example netlist

Vectron netlists normally have a .NET file extension.

*GND U1 7 U2 7
*VCC U1 14 U2 14
*CLOCK U1 10
*Q U1 6 U2 2 U1 9
*OUT U2 3
*B U1 4
*N00019 U1 3 U2 1
*N00013 U1 5 U1 8
*A U1 1 U1 2
Example part list
U1 14DIP300
U2 14DIP300

Verilog netlist format

Verilog netlists have the following characteristics:

  • Part identifiers, module identifiers, reference strings, node identifiers, and pin numbers are not checked for length.
  • Part identifiers, module identifiers, reference strings, node identifiers, and pin numbers must begin with a letter.
  • Part identifiers, module identifiers, reference strings, node identifiers, and pin numbers must all be unique. That is, none of these can share a name.
  • Legal characters for part identifiers, module identifiers, reference strings, node identifiers, and pin numbers are limited to:
A..Z a..z 0..9

If there are illegal characters in a part identifier, module identifier, reference string, node identifier, or pin number, the netlister converts them to legal Verilog names. This conversion uses the backslash character (\) to escape otherwise illegal characters. For spaces, the conversion uses the ASCII equivalent (#20).
Consider these examples:

This string....

converts to this...

____
RAS


\R\A\S\


A B


\A#20B


AggB


\A#20#20B


A#B


\A#B


A#20B


\A#2320B


A#23B


\A#2323B

For more information, see the Verilog netlist example.

Note: In cases where a net name is different from a port name, Capture uses aliases to associate the two. That is, if a wire with one net name is connected to a port with a different name, Capture creates an alias to associate the two components to the same net.

The alias takes either of the following forms:

alias_bit alias_inst1(NetName, PortName)
alias_vector alias_inst1(NetName, PortName)

Where:

NetName is the name assigned to the net.
PortName is the name assigned to the port.

If these aliases are used, they will appear at the beginning of the netlist.

Assigning a Verilog parameter to a component instance

Identifiers for parts, modules, part references, nodes, pins, and nets must not conflict with any Verilog reserved word. See Verilog reserved words for a list of reserved words.
You can specify Verilog parameters on component instances as properties, using this method:

  1. Assign the property Vlog_param to the component, using the following syntax:
Vlog_Param = Parameter_name:Parameter_type

Where:

Parameter_name is the name of the parameter to be specified in the netlist.
Parameter_type is the type of the parameter (for example, "integer," or "string").

Note: You can specify multiple Verilog parameters on a component instance, as well, by using the following format:

Vlog_ParamXX = Parameter_name:Parameter_type

Where:

XX is an integer that is unique to the parameter being defined.

  1. Assign a value to the declared parameter:

Note: Parameter_name = Parameter_value

Where:

Parameter_name is the name of the parameter to be specified in the netlist.
Parameter_value is the value of the parameter.

The parameter will appear in the netlist as:

\7400 U7(
 .A_A( IN1 ) ,
 .B_A( IN2 ) ,
 .Y_A( OUT ) ,
 .VCC( VCC ) ,
 .GND( GND )
) ;
defparam U7.Parameter_name = Parameter_value;

If the parameter value is a string, the netlister encloses it in quotes ("") in the netlist. If a parameter does not have a value, the netlister will report an error.

Support of global signals and creation of global module

The Verilog netlister connects to global signals using the global module "glbl". This distinguishes global signals from local signals. For example:

//Verilog global signals module
module glbl() ;
wire global;
...
endmodule
module schematic1() ;
...
wire global; //local alias for the global signal "global"
assign global = glbl.global;
...
ls04 i1(
.a(global),
...);
...
endmodule

By default, only power signals are considered global. Capture inserts the global module at the top of the Verilog netlist.
If your design is a PSpice A/DV design, Capture places the connections to the global signals under `ifdef VAN. This is so that the normal Verilog simulation will not get affected. For example:

`ifdef VAN
module glbl;
wire global;
...
endmodule
`endif
module schematic1;
...
`ifdef VAN
wire global; //local alias for the global signal "global"
assign global = glbl.global;
`endif
...
ls04 i1(
`ifdef VAN
.a(glbl.global),
`else
.a(global),
`endif
...);
...
Endmodule

Verilog netlists normally have a .V file extension.

Example Verilog netlist with power pins included
`timescale 1ns/1ps
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl;
 wire VCC;
 wire GND;
endmodule
module HALFADD ( X, Y, CARRY, SUM);
input X;
input Y;
output CARRY;
output SUM;
// SIGNALS
wire VCC;
assign VCC = glbl.VCC;
wire GND;
assign GND = glbl.GND;
wire N00032;
wire X_BAR;
wire N00034;
wire N5056796111;
// GATE INSTANCES
\74LS32 U1(
 .I0_B( N00032 ) ,
 .I1_B( N00034 ) ,
 .O_B( SUM )
 ) ;
\74LS08 U2(
 .I0_A( X ) ,
 .I1_A( N5056796111 ) ,
 .O_A( N00032 ) ,
 .VCC( VCC ) ,
 .GND( GND ) ,
 .I0_B( Y ) ,
 .I1_B( X_BAR ) ,
 .O_B( N00034 ) ,
 .I0_C( Y ) ,
 .I1_C( X ) ,
 .O_C( CARRY )
) ;
\74LS04 U3(
 .I_A( X ) ,
 .O_A( X_BAR ) ,
 .VCC( VCC ) ,
 .GND( GND ) ,
 .I_B( Y ) ,
 .O_B( N5056796111 ) ) ;
endmodule
module FULLADD ( SUM, X, Y, CARRY_OUT, CARRY_IN);
output SUM;
input X;
input Y;
output CARRY_OUT;
input CARRY_IN;
// SIGNALS
wire VCC;
assign VCC = glbl.VCC;
wire GND;
assign GND = glbl.GND;
wire N00011;
wire N00013;
wire N00023;
// GATE INSTANCES
\74LS32 U1(
 .I0_A( N00013 ) ,
 .I1_A( N00023 ) ,
 .O_A( CARRY_OUT ) ,
 .VCC( VCC ) ,
 .GND( GND )
 ) ;
HALFADD HALFADD_A (
 .X( CARRY_IN ) ,
 .Y( N00011 ) ,
 .CARRY( N00013 ) ,
 .SUM( SUM )
 ) ;
HALFADD HALFADD_B (
 .X( X ) ,
 .Y( Y ) ,
 .CARRY( N00023 ) ,
 .SUM( N00011 )
 ) ;
endmodule
Example Verilog netlist without power pins included
`timescale 1ns/1ps
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl;
endmodule
module HALFADD ( X, Y, CARRY, SUM);
input X;
input Y;
output CARRY;
output SUM;
// SIGNALS
wire N00032;
wire X_BAR;
wire N00034;
wire N5056796111;
// GATE INSTANCES
\74LS32 U1(
 .I0_B( N00032 ) ,
 .I1_B( N00034 ) ,
 .O_B( SUM )
) ;
\74LS08 U2(
 .I0_A( X ) ,
 .I1_A( N5056796111 ) ,
 .O_A( N00032 ) ,
 .I0_B( Y ) ,
 .I1_B( X_BAR ) ,
 .O_B( N00034 ) ,
 .I0_C( Y ) ,
 .I1_C( X ) ,
 .O_C( CARRY )
 ) ;
\74LS04 U3(
 .I_A( X ) ,
 .O_A( X_BAR ) ,
 .I_B( Y ) ,
 .O_B( N5056796111 )
 ) ;
endmodule
module FULLADD ( SUM, X, Y, CARRY_OUT, CARRY_IN);
output SUM;
input X;
input Y;
output CARRY_OUT;
input CARRY_IN;
// SIGNALS
wire N00011;
wire N00013;
wire N00023;
// GATE INSTANCES
\74LS32 U1(
 .I0_A( N00013 ) ,
 .I1_A( N00023 ) ,
 .O_A( CARRY_OUT )
 ) ;
HALFADD HALFADD_A (
 .X( CARRY_IN ) ,
 .Y( N00011 ) ,
 .CARRY( N00013 ) ,
 .SUM( SUM )
 ) ;
HALFADD HALFADD_B (
 .X( X ) ,
 .Y( Y ) ,
 .CARRY( N00023 ) ,
 .SUM( N00011 )
 ) ;
endmodule

VHDL netlist format

VHDL netlists have the following characteristics:

  • If the 1076-87 VHDL standard is selected, legal characters for node names are limited to:
    0..9 A..Z a..z _ (underscore)
    with the following limitations:
    • The first character is limited to: A..Z a..z
    • The last character restricted from: _ (underscore)
    • If the 1076-93 VHDL standard is selected, you can use special characters, VHDL reserved words, and names that begin with digits. To do so, delimit the name with backslashes (\) and precede any special characters—including "internal" backslashes (not the delimiters)—with a backslash. The following table contains some examples.

Object

Name

Problem

Solution

Node

signal

Reserved Word

\signal\

Node

SIGNAL

Case sensitivity

\SIGNAL\

Pin

Q\

Overbar

\Q\\\

Pin

R\E\S\E\T\

Overbar

\R\\E\\S\\E\\T\\\

Pin

12-GND

Leading digit, hyphen

\12\-GND\

For more information, see the 1076-93 VHDL standard, as well as the list of VHDL reserved words, and the VHDL netlist example.

Note: Do not name the data buses in your design in this format: datain1 [11..0], datain2 [11..0], and so on. Instead use this format for naming the data buses: dataina [11..0], datainb [11..0]. Because the VHDL netlister expands the data bits in the port map section and writes it as datain (111).

Schematic attributes in VHDL netlists

You can enter part or net attributes on your schematic for inclusion in the VHDL netlist in one of three ways:

  • You can enter attributes (properties) with your own user-defined types.
    To do this, when you assign a property to a part or net in the schematic, you define it thusly:
attribute name: name
attribute value: vhdl_type is value

So, for example, to enter a property for the user-defined type part_version, you assign the name and value as follows:

attribute name: my_part
attribute value: part_version is XC1.2

The resulting VHDL netlist would include the attribute as follows:
ATTRIBUTE my_part:part_version
ATTRIBUTE my_part of PA3 : signal is XC1.2

Note: If you do not define the property’s VHDL type in the value field, or if the VHDL type is not defined in the ATTRIBUTE.VHX file, Capture assigns the type “string” to that property.

  • You can enter attributes (properties) without a user-defined type.
    To do this, when you assign a property to a part or net in the schematic, you define it thusly:
attribute name: name
attribute value: value

So, for example, to enter a property without a user-defined type, you assign the name and value as follows:

attribute name: blackbox
attribute value: no_touch

The resulting VHDL netlist would include the attribute as follows:

ATTRIBUTE blackbox:string
ATTRIBUTE no_touch of PA3 : signal is true
  • You can enter attributes (properties) that are assigned types in the ATTRIBUTE.VHX file by matching the attribute name with an attribute type that is defined in that file.
    To do this, when you assign a property to a part or net in the schematic, you do not explicitly assign it a type and you use a name that is defined as a particular type in the ATTRIBUTES.VHX file. Thus:
attribute name: defined_name
attribute value: value

In this case, Capture checks the contents of the ATTRIBUTE.VHX file, locates the attribute name and associates the type with the attribute name.
So, for example, to enter a property and assign it a type as defined in the ATTRIBUTE.VHX file, you assign the name and value as follows:

attribute name: attribute_syn_preserve
attribute value: false

The property attribute_syn_preserve is defined as type “boolean” in the ATTRIBUTE.VHX file. Therefore, the resulting VHDL netlist would include the attribute as follows:

ATTRIBUTE attribute_syn_preserve:boolean
ATTRIBUTE attribute_syn_preserve of PA3 : signal is false

Note: The ATTRIBUTE.VHX file is a text file that you can edit to define your own attributes and associated types.

Example

This netlist was created with no options selected. VHDL netlists normally have a .VHD file extension.

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY EX6B IS PORT (
X : IN std_logic;
Y : IN std_logic;
CARRY : OUT std_logic;
SUM : OUT std_logic
); END EX6B;
ARCHITECTURE STRUCTURE OF EX6B IS
-- COMPONENTS
COMPONENT \74LS32\
PORT (
I0_A : IN std_logic;
I1_A : IN std_logic;
O_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
O_B : OUT std_logic;
I0_C : IN std_logic;
I1_C : IN std_logic;
O_C : OUT std_logic;
I0_D : IN std_logic;
I1_D : IN std_logic;
O_D : OUT std_logic
); END COMPONENT;
COMPONENT \74LS08\
PORT (
I0_A : IN std_logic;
I1_A : IN std_logic;
O_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
O_B : OUT std_logic;
I0_C : IN std_logic;
I1_C : IN std_logic;
O_C : OUT std_logic;
I0_D : IN std_logic;
I1_D : IN std_logic;
O_D : OUT std_logic
); END COMPONENT;
COMPONENT \74LS04\
PORT (
I_A : IN std_logic;
O_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
I_B : IN std_logic;
O_B : OUT std_logic;
I_C : IN std_logic;
O_C : OUT std_logic;
I_D : IN std_logic;
O_D : OUT std_logic;
I_E : IN std_logic;
O_E : OUT std_logic;
I_F : IN std_logic;
O_F : OUT std_logic
); END COMPONENT;
-- SIGNALS
SIGNAL X_BAR : std_logic;
SIGNAL N00037 : std_logic;
SIGNAL N00035 : std_logic;
SIGNAL GND : std_logic;
SIGNAL VCC : std_logic;
SIGNAL N5056796111 : std_logic;
-- GATE INSTANCES
BEGIN
U1 : \74LS32\ PORT MAP
I0_A => 'Z',
I1_A => 'Z',
O_A => OPEN,
VCC => OPEN,
GND => OPEN,
I0_B => N00035,
I1_B => N00037,
O_B => SUM,
I0_C => 'Z',
I1_C => 'Z',
O_C => OPEN,
I0_D => 'Z',
I1_D => 'Z',
O_D => OPEN
);
U2 : \74LS08\ PORT MAP(
I0_A => X,
I1_A => N5056796111,
O_A => N00035,
VCC => VCC,
GND => GND,
I0_B => Y,
I1_B => X_BAR,
O_B => N00037,
I0_C => Y,
I1_C => X,
O_C => CARRY,
I0_D => 'Z',
I1_D => 'Z',
O_D => OPEN
);
U3 : \74LS04\ PORT MAP(
I_A => X,
O_A => X_BAR,
VCC => VCC,
GND => GND,
I_B => Y,
O_B => N5056796111,
I_C => 'Z',
O_C => OPEN,
I_D => 'Z',
O_D => OPEN,
I_E => 'Z',
O_E => OPEN,
I_F => 'Z',
O_F => OPEN
);
END STRUCTURE;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY FULLADD IS PORT (
SUM : OUT std_logic;
X : IN std_logic;
Y : IN std_logic;
CARRY_OUT : OUT std_logic;
CARRY_IN : IN std_logic
); END FULLADD;
ARCHITECTURE STRUCTURE OF FULLADD IS
-- COMPONENTS
COMPONENT \74LS32\
PORT (
I0_A : IN std_logic;
I1_A : IN std_logic;
O_A : OUT std_logic;
VCC : IN std_logic;
GND : IN std_logic;
I0_B : IN std_logic;
I1_B : IN std_logic;
O_B : OUT std_logic;
I0_C : IN std_logic;
I1_C : IN std_logic;
O_C : OUT std_logic;
I0_D : IN std_logic;
I1_D : IN std_logic;
O_D : OUT std_logic
); END COMPONENT;
COMPONENT EX6B PORT (
X : IN std_logic;
Y : IN std_logic;
CARRY : OUT std_logic;
SUM : OUT std_logic
); END COMPONENT;
-- SIGNALS
SIGNAL N00015 : std_logic;
SIGNAL N00013 : std_logic;
SIGNAL N00025 : std_logic;
SIGNAL VCC : std_logic;
SIGNAL GND : std_logic;
-- GATE INSTANCES
BEGIN
U1 : \74LS32\&#9;PORT MAP
I0_A => N00015,
I1_A => N00025,
O_A => CARRY_OUT,
VCC => VCC,
GND => GND,
I0_B => 'Z',
I1_B => 'Z',
O_B => OPEN,
I0_C => 'Z',
I1_C => 'Z',
O_C => OPEN,
I0_D => 'Z',
I1_D => 'Z',
O_D => OPEN
);
halfadd_A : EX6B PORT MAP(
X => CARRY_IN,
Y => N00013,
CARRY => N00015,
SUM => SUM
);
halfadd_B : EX6B PORT MAP(
X => X,
Y => Y,
CARRY => N00025,
SUM => N00013
);
END STRUCTURE;

VST Model netlist format

This format file produces netlists for modeling with OrCAD's Digital Simulation Tools 386+. See the Digital Simulation Tools User's Guide for details.
VST Model netlists have the following characteristics:

  • Part names, module names, reference strings, node names, and pin numbers are not checked for length.
  • Node numbers and pin names are not used.
  • All ASCII characters are legal.
    For more information, see the VST netlist example.
VST netlist constraints

When you create a VST Model netlist, be sure you include the OrCAD-supplied VSTGATES.OLB, VSTRAM.OLB, VSTROM.OLB, and VSTOTHER.OLB part libraries in your project. You can use only the parts provided in these libraries to create the schematic folder.

VST pipe commands

Lines of text may be placed on your schematic page to be included in the VST Model netlist. Select the Text command from the Place menu to place the text on a schematic page.
Each line of text must start with the pipe character (|). The first line must be:

|VST_MODEL

This tells Capture to extract the information in the following lines of text when generating a VST Model netlist. The remaining lines can contain a header, comments, and directives compatible with OrCAD's Digital Simulation Tools 386+ Add Device Model device modeling language. For details on the Add Device Model Language, see the Digital Simulation Tools User's Guide.

WinBoard netlist format

Ivex WinBoard netlists have the following characteristics:

  • Part names are not checked for length.
  • Module names are not checked for length.
  • Reference strings are not checked for length.
  • Node names are limited to eight characters.
  • Node numbers are limited to five digits following the "N" prefix.
  • Pin numbers are not checked for length.
    For more information see the WinBoard netlist example.
Example

WinBoard netlists normally have an .NET file extension.

WINBOARD 1.01
`I "ORCAD CAPTURE 7.20";
`F "D:\ORCAD DEMO\CAPTURE\NETLIST UPDATES\DESIGN1\FIG_B-01.SCH";
`T "Generic Netlist Example";
`S "Thursday, November 12, 1998";
`C "OrCAD-01";
`R "A";
`C "OrCAD";
`C "9300 S.W. Nimbus Ave.";
`C "Beaverton, OR 97008";
`C "(503) 671-9500 Corporate Offices";
`C "(503) 671-9400 Technical Support";
`M 14DIP300,,74LS00,6CB84CBA,U1,C,GR1
(1 A IN A1)
(2 A IN A1)
(3 N00019 OU A1)
(4 B IN A1)
(5 N00013 IN A1)
(6 Q OU A1)
(7 GND PO A1)
(8 N00013 OU A1)
(9 Q IN A1)
(10 CLOCK IN A1)
(11 ?1 OU A1)
(12 ?2 IN A1)
(13 ?3 IN A1)
(14 VCC PO A1)
;
`M 14DIP300,,74LS32,6E46169D,U2,C,GR1
(1 N00019 IN A1)
(2 Q IN A1)
(3 OUT OU A1)
(4 ?4 IN A1)
(5 ?5 IN A1)
(6 ?6 OU A1)
(7 GND PO A1)
(8 ?7 OU A1)
(9 ?8 IN A1)
(10 ?9 IN A1)
(11 ?10 OU A1)
(12 ?11 IN A1)
(13 ?12 IN A1)
(14 VCC PO A1)
;

If you have any questions or comments about the OrCAD X platform, click on the link below.

Contact Us