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Section 9 – PCB Design: Analog Routing

This is the ninth section in the back-to-school series for PCB Designers and those who may want to know more about it. 


Analog Routing

Oh, students of the PCB Design future, this is where it gets real. The digital data is often coupled to the real world where logical ones and zeros are not enough. In between those two, there are shades of grey which are filled in with analog circuits. That data stream is converted into digital approximations and all of a sudden, ‘Bam ’ room for lots of little transmitters and receivers!

“Summing it all up: When it comes to analog layout, impedance is the name of the game. The transmission lines become components unto themselves. Placement is built around the traces rather than the other way around. You don’t really place and route so much as build a route incorporating the components along the way.”

Dependence on keeping the impedance constant is a strong incentive to use surface-mount components and make the connections on the same layer using microstrip or coplanar waveguides. These transmission lines are noisy by nature so our instinct is to route them on an inner layer where they can be sandwiched between a pair of ground planes as a stripline trace. That plan is preferable to having a long trace on an outer layer and sometimes, you just can’t help transmission lines that cross over one another.

The best case is when you can create a placement where all of the RF connections are between pins that are as close as the assembly and test rules allow. When a choice has to be made to lengthen one trace or another, defer to the receive (RX) chain allowing the transmission (TX) line to have the longer trace. Receivers have big ears and small mouths while transmitters are loud mouths that are relatively hard of hearing. Obviously, the two do not make good neighbors.

Estimating impedance for a given stack-up

A few dimensions and one constant are what determine the characteristic impedance of a transmission line. The dielectric constant (Dk) is a key factor that determines propagation delay as well as the loss tangent. All insulators have a dielectric constant. For example, air has a Dk of one. Standard FR4 material has a Dk of around 4.5 and this varies over frequency, temperature and, of course, the exact type of material since FR4 covers a lot of ground.

On an outer layer, there is one dielectric thickness of note and that is the distance to the copper plane below the transmission line. The electrical and magnetic fields live primarily in this space. An elegant design will keep them there while a dodgy design will cause them to spread out. In order to achieve the typical 50 ohm impedance, the simple formula is to make the microstrip trace width equal to the dielectric thickness.

That can be an issue if the dielectric material is very thin as it will be when you use a micro-via. Bear in mind that you might use Layer-3 as the reference plane and keep Layer-2 free of copper. Anything on Layer-2 will disrupt the impedance and also get massive coupling between the transmission line and anything in that dielectric space. Take the trace width of the microstrip and multiply it by three to get a good safe distance for any metal on the cleared layer(s).

Selecting the Correct Dielectrics. It’s All in the Materials.

The other key factors for controlled impedance are the thickness of the dielectric material and the trace width. The actual z-height of the copper, coating materials and fiber weave considerations are secondary effects that come into play as the rise and fall times increase. There are other metrics such as loss tangent and the coefficient of thermal expansion (tg) of the material to evaluate.

“Everywhere you go, there’s an equivalent material to cut in.”

At that point, you may have to consider exotic materials with trade names like GETEK, Rogers or Megtron. Doing so will require a different approach to rough impedance calculations. In all cases, you MUST get your PCB fabrication vendor(s) into the conversation sooner than later. There are a lot of choices and many of them are regional. Everywhere you go, there’s an equivalent material to cut in.

Analog traces on a circuit board

Figure 1. Image Credit: Author - Analog traces like to be sequestered.

The analog lines are purposefully wide in Figure 1. This was done by selecting a 0.7 mm dielectric thick. Given the dk, the 50 ohm lines calculated out at a width that is pretty close to the width of the typical pads. This old-school through-hole board also opens up all of the solder mask over the vias to provide a probepoint or potential rework path. Analog technicians are no stranger to scraping away a little bit of solder mask.

Also not the absurd measures taken every time one of the micro-strip traces takes a dive into the stripline zone. Not one ground via but four looking almost like a little SMA connector. We’re making a coax in the z-axis to shield the via. As the trace approaches the ground vias, the trace narrows and the ground pour converges creating a coplanar waveguide for the segment connecting to the signal via. The trace is meant to be coplanar as it travels over the gap between the ground planes and the signal via. So let’s explore the inner workings.

Moving on to stripline traces, the deal is that there are two plane layers, one above and one below the trace. Use the same one-to-one formula but look at the stack-up and make sure you are considering the thinnest dielectric for the rule. Some routing layers in the stack up make this simple because they are symmetric. (1)

When routing a differential pair, the same rule of thumb applies to the two traces but only if they are separated by a minimum of three times the trace width. Those are considered uncoupled differential pairs. In this case, the impedance value doubles so the one-to-one ratio that gave you 50 ohms now is approximately 100 ohms.

As the two traces get closer and become loosely coupled (between 3x and 1x trace width) or tightly coupled (1x trace width and below) the impedance goes down so the two lines have to be thinner than the dielectric to get back to the common 100 ohm impedance. Again, this drives the PCB into line-width manufacturability issues. For this reason, I’ve seen loosely coupled and uncoupled differential pairs on the majority of board designs.

Layer Assignment: Typical Routing Solutions Based on the Number of Layers.

This 14-Layer stack-up provides four internal routing layers. A 12-Layer version of this one would remove layers 6 and 9 which are ground planes between the power planes and the inner 2 routing channels. Layers 5 and 10 would be the choice for low-speed traces while Layers 3 and 12 would be safer for high speed and RF routing. That’s because you would continue to have ground planes above and below the transmission lines rather than a ground plane and a power plane. Best case in that regard is a voltage match between the logic and the power plane.

Via layers on a multilayer circuit board

Figure 2. Image Credit: Author - A so-called 3 N 3 stack up where N is equal to the span of the core via.

Additionally, cutting out layers 4 and 5 yields a 10-Layer board. This price point eliminates the ground plane between the inner layer traces. This is called a Ground-Signal-Signal-Ground stack. The notion is to use the two routing layers orthogonally to each other with the aim of not running the two traces broadside, one over another. Some of that may be inevitable as you fan-out a dense device or connector.

Ten layers is a sweet spot. An 8-Layer board will take you back to Ground-Signal-Ground but you will only have two inner layers for routing. At six layers and below, we’re not really distinguishing a layer for a certain purpose. All the layers are ground layers. Then they’re component layers, power planes, routing layers and the usual decorations. Those low layer-count boards can be tricky. You always have to bear in mind what is above and below the layer you’re working on.

RF Modules - A Solution in a Box

A popular solution is to use RF modules that include a radio chip with the required bias circuits and matching networks in a rectangular package with pins around the edges. RF modules are similar to QFN packages but may have SMD pins that are larger and located a little more in-board. Depending on the frequency, a module, the substrate can be regular FR4 or a high-speed/low loss version on up to ceramics and other exotic materials.

Front End Modules (FEMs) combine all of the TX and RX circuits in a convenient package. Starting at the RF input pin, they may include a low noise amplifier, filters, a duplexer, switches, a diplexer, the antenna matching network, the power conditioning, and the final stage amplifier leading to the TX out pin. It all fits under a nice RFI shield to help get through FCC regulations.

Flow of circuit components yielding RF Transceiver

Figure 3. Image Credit: EE Online - You can cobble the whole thing together with various components or get an off-the-shelf solution that takes most of the risk out of the equation.

Summing it all up: When it comes to analog layout, impedance is the name of the game. The transmission lines become components unto themselves. Placement is built around the traces rather than the other way around. You don’t really place and route so much as build a route incorporating the components along the way.

Graduate School Zone

Maintaining impedance through the whole analog chain is easier if the width of the trace and the SMD pads are equal or very close in width. That will call for relatively small pads and wide traces. A narrow trace entering a big pad creates a discontinuity. Meeting the impedance geometry will mean having a thicker dielectric between the transmission line and the reference plane.

As I mentioned in the part about impedance estimation, that plan is in direct conflict with typical HDI design rules that call for thin dielectrics to meet the aspect ratio design guideline of the microvia structure. The working solution in that case is to cut a channel in the ground plane on layer-two right below all of the transmission lines and use layer-three or even further into the board.

The width of the channel in the ground plane should match the metal pull-back on the trace layer, normally 3x the trace width. That way, a line of vias can be dropped along the length of the trace and tie the actual ground plane to the component layer. The saving grace is that analog circuits are typically not the dense part of the board so you should have layers to spare. That is assuming that the other parts of the board are the reason HDI technology is in use to begin with.

(2) A stack-up is symmetric when it is a mirror image from the center line outward. In addition, the three layers that make up a Ground-Signal-Ground routing channel would also have equal dielectric thicknesses surrounding the trace in the z-axis. Boards are constructed out of core materials and prepregs so just as often, the thickness will vary. The main point of symmetry is to avoid PCB warpage or other similar mechanical variances.

Next - Section 10 – PCB Design: Flex Circuits

About the Author

John Burkhert Jr is a career PCB Designer experienced in Military, Telecom, Consumer Hardware and lately, the Automotive industry. Originally, an RF specialist -- compelled to flip the bit now and then to fill the need for high-speed digital design. John enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. You can find John on LinkedIn.

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