This is the fourth section in the back-to-school series for PCB Designers and those who may want to know more about it.
- Component Placement
- Driving the Component Placement With the Schematic Diagram
- Verifying the Logic
- Floorplanning - Like Organizing a City Into Neighborhoods
- Analog Component Placement - How to RF
- Graduate School Zone
If your aim is to become a full-stack developer, you’re going to be capturing the logic in a schematic diagram. Excuse me while I back-track a little bit. Most tutorials would make this chapter one but here we go. When I first started doing the layout, the electrical engineers handed over a hand-drawn sketch and the CAD people generated all of the symbols, married them to the footprints, and created the whole schematic from there. It was a chance to decompress from the previous board while getting familiar with the next one.
Then, schematic capture on CAD tools became a part of the EE curriculum and the task became their job. Time marches on and now, a lot of PCB Designer opportunities are asking for this skill once again. Some are also asking for us to do 3D mechanical engineering as well. Welcome to the renaissance! A degree of some kind is more than likely to be desired as we go forward.
Whatever the case, the schematic is where we develop the connections between devices. It is also a potential place to set up some of the design guidance. For instance, components may be grouped into functional sections that are kept in close proximity and also kept separated from other circuits.
The placement guidance may be based on what goes inside of an EMI shield or clustered around the primary devices. This can be in the form of attributes assigned to individual components or simply rectangles around sections or entire pages of the schematic with a label describing the properties and physical locations around the board.
Figure 1. Image Credit: Bois83 - A typical schematic symbol for an analog chip.
In addition to driving placement, general routing rules may also be captured in one way or another. While we may not know the actual geometry of a transmission line at this stage, we can at least assign the impedance requirements to the nets so that they may be considered during placement. When you’re putting this additional information into the schematic in the form of a local note, it’s good to have a consistent approach that makes all of the information of this type searchable. Begin each piece of data with the words “Layout Note” or something similar.
Busses of all types can be established by the use of common net names. The actual length matching requirements may also be added but this is often left to the layout. The main idea is to give the general framework of the board and allow the designer to proceed from there. That’s not to say that it can’t be taken further to the point of establishing the location of each bypass capacitor by calling out the associated reference designator and pin number of the device pins next to each cap.
A block diagram is useful for establishing the floorplanning and placement parameters from a high level. If the board is complex enough to warrant a block diagram, chances are good that a power tree will also come in handy. A power tree begins with the root voltage at the top and spreads out through the various power supplies and voltage dividers down to each domain. The purpose of each voltage node is included along with the expected current consumption. If you’re going to add only one extra piece of intelligence, the power tree would usually be the most useful to capture for posterity.
Figure 2. Image Credit: Bois83 - Layout of the analog chip, see figure 1.
In addition to providing the high-level layout information, the Bill of Materials and the net-list are both extracted from the schematic. This is, after all, the intrinsic purpose of the schematic diagram. It’s easy to make little mistakes that can affect the output. Most mistakes are related to the misuse of a grid when generating or placing symbols and wires. Even if you’re not capturing the logic, here is where you can save the day, so to speak.
The most common problem I see is a wire just missing the pin. It looks connected but is not. Any two-pin component where only one pin is connected is a suspect. The second most common issue is a typo in a net name. Two nodes with identical net names except one has CLK and the other has TCK in the name should be reported back to the person who captured the schematic, even if you’re the one.
Always go through the pages of the schematic prior to digging into the layout. Wise engineers will want to capture their instructions for posterity. You may find out that two resistors are optional and that their common pins should overlap to create a “poor man’s switch.” with three pins made from four. Select-at-test component values or the use of zero ohm resistors are earmarks of a well-thought-out schematic. Take as much context as you can from the presentation, especially with analog circuits. Did I mention that I’m skipping the part about schematics? Let’s get on with placement.
Floorplanning starts with one part. Which part will depend on the nature of the board. A digital board is likely to have a chip or a chip-set that dominates the landscape. The designer would be well served to work from the center outward. Make good use of the link-budget to prioritize which peripheral components get to be near the main device.
Memory devices usually get the first priority. DDR comes before flash. Crystals and bypass capacitors want to be kept close to their respective pins. The power to the bias pins that makes all of the switching happen comes directly from the bypass caps. The power supply’s job is to recharge those caps. Even so, power supplies work best when they are placed near their loads.
It’s really only the odd sensor or radio chip that doesn’t want to be close to the processor. Sensors and antennas thrive in the boondocks. The PCB edge isn’t always the quietest location but a good place to start. Context matters. The optimum location for the analog circuits depends on the rest of the chip-set.
It’s not unusual for an RF device to be housed inside a faraday cage. Designing each analog circuit as a compact rectangle with room around each circuit for shield walls gives you that option. RF connectors are a special breed with a single signal pin surrounded by ground pins. The next part in the chain is usually a blocking capacitor.
Figure 3. Image Credit: Author - Analog boards like good fences. This was a rapid development system where the wide strips were for walls that could be screwed into the housing right through the PCB.
One of the most common features in an analog circuit is a pi pad. It takes three elements to make one; a shunt resistor then a series resistor and then another shunt resistor. When you see that combination on a schematic, keep the group packed together. Op amps are another common circuit. The key to a good op amp circuit is the feedback resistor which straddles the negative side of the input and output pin. That loop must be kept short.
The other short loop will be the bypass or decoupling capacitor; sometimes called a decoupling cap. That one goes from the voltage pin to the ground. Assuming surface mount components, routing the bypass cap starts at the power via with a wide trace that passes through the bypass cap and into the power pin. Via-in-pad is also acceptable but the via goes on the cap’s pin rather than the voltage pin of the device.
I went into specifics about the routing from the cap to the power pin because stubs can be a problem. They can also be a solution to a problem. Adding a little bit of extra metal along an RF transmission line can be used for impedance matching. There can be more than one of these wide spots carefully placed along the trace.
Components are not attached to the stub but you might want to consider it a component. The footprint would be a single pin with no associated part sort of like a test point except with a shape instead of a circle. Fine-tune the radio may require lengthening or shortening the stub. Little slivers of extra metal are left floating at the end of the stub so the tech can create a solder bridge or use a metal tab to solder it from the stub to the extension.
Hardworking components have high junction temperatures. Spreading them out helps dissipate the thermal energy that they generate. Heat is detrimental to reliability and concentrated hot spots will throttle the system until it no longer works as intended. Space that is plated with ground shapes that are perforated with vias are a hot component's best friend.
Harsh environments and Chip-On-Board applications will benefit from underfill. It is best to have two or more sides accessible for the underfill nozzle. Reworking BGA footprints requires clearance on all four sides for the tool. Either way, this area can be set aside as part of the footprint’s courtyard.
Every PCB is going to be different. Getting off to a good start involves going online and browsing for the devices to find data sheets and application notes. That works as a baseline that you can defend when questioned about placement decisions. Not all distributors update the drawings so it’s best to get it from the actual vendor if possible.
Figure 4. Image Credit: - Oversized SMT pads and underfilled devices are a characteristic of high-reliability PCBs. A bead of adhesive around the connectors is another insurance policy.
- IPC-A-610: Acceptability of Electronic Assemblies
- IPC-CM-770 Printed Board Component Mounting
- IPC-SM-780 Component Packaging and Interconnecting
- with Emphasis on Surface Mounting
- IPC-SM-782 Surface Mount Design and Land Pattern Standard