This is the fifth section in the back-to-school series for PCB Designers and those who may want to know more about it.
- Fan Out Studies
- Miniaturization Effects on PCB Design
- Shaping Up the Power Planes
- Graduate School Zone
Determining the layer-count and the via construction are the main goals of a fan out a study. The same device that was at the root of the floorplanning study is likely to be the one that drives the layer count and overall board construction. Those worst-case geometry components are sometimes the only device of that type that drive the rest of the criteria including PCB price and lead-time. After solving for that one pain point, the rest of the layout is relatively easy.
The easy ones are traps! Remember the words, “Fan OUT” and add vias accordingly. A well-planned fanout will get every signal to pass through the ground plane in its own void in the copper. When two vias share the same hole through the copper plane, there may be magnetic coupling that affects the integrity of the circuit. Fine-pitch connectors and quad-packs need some breathing room for the fact that the vias will be larger than the pins. Plan for it during placement.
Figure 1. Image Credit: Author - Isolated differential pairs fanning out from a connector.
High-speed differential pairs like to be routed on an inner layer to reduce spectral emissions. A copper flood of ground further isolates each pair. Note that the signal vias are gathered towards one another because that’s what the pin pitch of the connector allows. Other signals and power/ground connections follow a more familiar BGA fan-out.
The top layer, shown in blue is used to reduce the via-count by routing on the primary component layer. This opens up the channels for the second row up to where all of the high-speed differential pairs are launched on Layer-3 shown in cyan. Furthermore, the third row and all subsequent rows fan-out in an upward direction to give more space to the diff-pairs.
The exception to the “fan-up” is the ground vias. Not only do they fan-down, but some of the ground pins on the second row also have two ground-vias so that there is one ground-via near each high-speed signal pin. The ground pins on the outer row fan-out straight down rather than at an angle. This allows access to pins in the interior of the connector without using a via.
The never-ending trend is for smaller components. The main goal of the component package design is to spread out the chip’s connections to a more reasonable pitch. Generation after generation, the pitch decreases while the pin-count goes up. This has continued to the point where the Chip Scale Package (CSP) has become a normal technology.
CSP is defined by the ratio of the silicon to the package. To begin with, the ratio was set at 1.2:1 where the whole package was only nominally larger than the die itself. Those package sizes persist while the dice have gone through further shrinkage nodes down into the single-digit nanometer scale for individual features.
Chip Scale Packaging is, by definition, High Density Interconnect where micro-vias are the primary inter-layer conduit. The two-layer substrate that houses the chip is quick to design and fabricate. The resulting component package is small. That’s good for Marketing but not so great when you’re trying to design a robust PCB.
Figure 2. Image Credit: Murata - Capacitors are shrinking too. 0201 packages are common, 01005 packages have been around for almost 10 years. Introducing the 008005 as the next tiny thing. Translated, that’s 10 mils long and 5 mils
The PCB Designer eventually becomes responsible for the job traditionally handled by the substrate. The silicon die type known as a flip chip will be attached to a substrate and the connections will be passed through a via to the SMD pads.
The alternative to a flip chip is die-attach done having the copper slug attached to the bottom of the die. The solid metal base is reflowed inside a cavity in the substrate. Then, wire bonds are used to connect the upward-facing pins of the chip to the substrate. The only expansion of the pin-pitch would come from the wirebond cage in that situation.
Even when the chip vendor uses an interposer to spread out the pins of a flip-chip, the results may require High Density Interconnect to fan-out. HDI is an expensive and time consuming process. (1) A board could have twenty devices with only one of them being too fine-pitched to get done with plated though-hole vias.
“...the hot new technology is copper pillars in place of the balls of solder”
Chip makers continue to push the limits of HDI technology. Leading edge ball grid array (BGA) packages have a pitch of 350 microns; not quite 14 mils center to center.. At that rate the pads will be solder mask defined. The metal pad size defined by the smallest via the fab shop can produce.
The fab shops have to get better at it. Shrinking the package further still, the hot new technology is copper pillars in place of the balls of solder on a standard flip-chip. The via-in-pad is the foundation for all of these technologies. It’s the light blue part of figure 2 that remains mostly the same in spite of the shrinking pins.
Figure 3. Image Credit: Dupont - It seems like every time the industry moves to the next smaller node, the burden is on the PCB design and fabrication people to solve the technical challenges.
According to Dupont, this maturing technology allows the substrate packaging to be reduced by as much as 300%. What are you going to do when the pin pitch gets down to 135 microns? That’s pretty ridiculous. Meanwhile, Murata is making 01005 size chip caps look huge with their 008004 packages.
More than likely that one device is going to drive extra lamination cycles to build up the number of micro-vias while the rest can be done at a lower cost. Each additional layer of micro-vias adds a measurable percentage to the cost. I’m driving this home because we keep score with money and the PCB can be a substantial part of the Bill Of Materials cost.
These cost-driving components are typically ball grid array (BGA) packages. A quad-flat-pack-no-lead (QFN) package can have the same 0.5 mm or 0.4 mm pin-pitch and not require an HDI stack-up. A little communication with the stakeholders including management and procurement might be enough to change the value proposition. If nothing else, it lets them know that you have your head in the right place. If you have time to do a little searching to see if there is a viable substitute, so much the better.
Figure 4. Image Credit: Author - A few examples of QFN and QFP packages. In this six-layer HDI stack-up, the primary component layer is also the horizontal routing layer.
Fan-out studies do not require every component to be placed on the board right away. The challenging device(s) can be done in isolation. Since the traces are not routing away from the cluster of components that complete the chip, the whole thing can be moved without much effort.
One method that I’ve found successful is to place each page in its own off-board area. As each page is complete, draw a rectangle around the parts and label them with the schematic page number and the circuit description that is usually provided on each page. It’s not that much work to present the components as they are organized in the schematic. Floor planning is easier for those who are also involved when the circuits are identified.
Use a text size that is still visible even when the whole board space is on the screen; just a few words for a brief description. Getting all of those chips organized into their optimum placement allows you to explore the connections between each function with higher confidence. Priority will go to the length of matched groups and any controlled impedance nets.
Power distribution starts with the floor planning and gets proven out during the fan-out study. It may take some iterating to find the most advantageous power plan. Making things better along the way is a central part of PCB design. That’s why we want to do a fan-out study before knitting everything together.
Colorizing various voltage domains is important since you want to keep power planes tidy. If you have a power tree, then assigning colors that are meaningful is a great idea. Using shades of deep purple all the way to pink to show relative power requirements is my favorite. If you also happen to have various ground domains, try shades of green for the cleaner ground and brown when it gets to the dirty digital stuff. Sorting the component clusters by their return path is every bit as important as keeping like voltages together.
Generally speaking, high voltage requires extra attention when it comes to spacing. It’s the amps and milliamps that matter in terms of the width of the trace or shape. Current capacity in tight areas can be augmented by going vertical. Use another shape on an additional layer or more layers until the total copper weight is sufficient to manage temperature rise. Make sure the shapes are tied together with multiple vias at the source and the loads.
A power-management integrated circuit (PMIC) will have a concentration of current with all of the output pins around the edges. The area between the output pins and the inductors are particularly problematic when it comes to noise. The size of the inductors compared to the pitch of the pins creates a situation where the shapes in between will look like a fan as they spread out from the pins.
The pain-points come into a clearer view as the power shapes are fleshed out. One main goal of the fan-out study is to reduce churn during the routing phase. If you are fortunate enough to have a power integrity engineer in-house, getting their opinion, or better yet, simulation results is a valuable step. The larger the power-tree, the more this type of interaction becomes necessary.
Power integrity is the main source of drama in mobile hardware. Correcting the power distribution network will solve issues with battery life, thermal degradation, and overall performance. Most every design will have some compromises. Giving the devices clean and plentiful power will help cover for other shortcomings.
Given the trend towards miniaturization, we’re going to have to work harder to manage the junction temperatures from the silicon outward. There will be a little less current to pump out but in a lot smaller space. Adding the higher speeds of the next generation of devices to the high current density situation only compounds the problem. We want “more” so there’s no going back. Look forward to lots of simulation and iteration. Here it comes.
(1) HDI is a construction method that allows for smaller vias that traverse one layer-pair at a time. It makes it possible to use via-in-pad without too much extra work. It is a game-changer when you don’t have to allow extra room for fan-out vias during placement. The traces start on an inner layer that is best suited for the type of signal. Note the stack-up diagram at the end of Section one.
- IPC-7094A: Design and Assembly Process Implementation for Flip Chip and Die-Size Components
- IPC-7095C: Design and Assembly Process Implementation for BGAs