This is the twelfth section in the back-to-school series for PCB Designers and those who may want to know more about it.
- How to Design For Test
- Placing Test Points Prior to Routing
- Single-Sided Test Access is Preferred
- Graduate School Zone
We design for a lot of different factors. One of the key factors is to be able to isolate and replace defective components. Beyond non-functioning parts, defects can result from polarized components that were placed in the wrong orientation, incorrect part values, and bad solder joints. Solder joints can go bad in numerous ways creating opens or shorts, the worst of which are latent defects. They look good until they don’t.
Test access isn’t cheap. It takes up valuable PCB space. More than just the size of the probe point, the points have to clear other components, as well as maintain a spacing from one test point to another. Tall components require extra spacing.
Oftentimes, the goal is to look at a few key nets for testing by hand. These are touch-points so a larger reference designator and perhaps a functional description taken from the net name would make the board more user-friendly. Those cases may include terminals where a meter can be hooked to a physical pin. In that case, they are included in the schematic and placed along with the other components. The test hooks are usually surface mount but also come in through-hole versions.
Figure 1. Image Credit: Author - Basket handle loops can be used to clip the probe hook to the ground or other net.
In-circuit test points should be distributed across the board without being concentrated in any one area. Even placing them in a nice line of test points with more than the required spacing can be a problem. The bed-of-nails test fixture puts pressure on the board so a test point pattern that meets the written design criteria can be rejected by the test engineering team.
If “they” had their way, I’d put all of the test points in a special pattern over and over and then place and route the board around that. To be honest, that’s over-stating it but I bet you could find people who would get behind a one-size fits all array of test points. A good ICT plan cannot be an afterthought. Placement and fan-out studies are more tedious when incorporating test points. The pay-off is that it is much more tedious to graft them onto an existing layout where everything is already buttoned up.
Figure 2. Image Credit: Author - The secondary side of the board is usually a better place for the ICT points if you’re only using one side.
The goal is to have a test point on every net. But wait, there’s more! Distribute a handful for each power domain and salt the whole board with ground test points. It got to the point where I don’t like resistors below a certain value because the TE wants two test points on either side of those resistors; something about the resistance of the probes themselves. Ok, we need to plan ahead for these things.
It would be nice if you could get all of the test points on one side of the PCB. A regular bed-of-nails is expensive. A clamshell fixture is really expensive. Another cost driver has to do with the size of the test points. If you could set your grid to 2.54 mm and then use every other point and stagger each row, they might like the test plan. Welcome to the real world.
Life is a little better when the plan is to use a flying probe head. For one thing, you can do a revision of the board and they can reprogram the machine to find the new test point locations. The probe points can be a little smaller and it isn’t such a big deal to distribute them in an irregular way. The trade-off is that the flying probe machine takes longer to complete each board as it goes around with two robotic probes and checks each connection one-by-one.
Getting a little more real is giving up on 100% coverage and only testing power and ground nets. The thought process is that there are too many connections for the amount of space between the components anyway. Add in the percentage of traces where a test point would be too much of an impedance discontinuity and all that’s left is the power and ground planes plus a few points of interest.
Figure 3. Image Credit: Author - Alternative test points can take several forms. This type allows the tester to hook the probe to the test point to have a free hand.
As density becomes too much for even that, the fall-back plan is more about functional testing. Boundary scan via a JTAG connector. Boards that fail are set aside. If the tech can’t troubleshoot and repair the board in a few minutes, it’s not worth the effort in some cases. The factory wants the product to flow with a minimum of human hands on it. It seems wasteful but hand-operations aren’t a money maker. So called second-op tasks that happen after the PCB comes out of the reflow oven have to be eliminated for mass production. It’s a cruel world.
- IPC-2515 Bare Board Product Electrical Testing Data Description
- IPC-ET-652 Guidelines and Requirements for Electrical Testing of Unpopulated Printed Boards
- IPC-356 Bare Substrate Electrical Test Data Format
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