Section 6 – PCB Design: Digital Routing

This is the sixth section in the back-to-school series for PCB Designers and those who may want to know more about it. 


Digital Routing

There’s routing and then there’s “routing.” Before any of that begins, it is necessary to identify any connections that require special handling. As I outlined in the chapter on fan-out, there’s a progression of interfaces to consider. A group of nets may have a maximum length and would also be tightly matched within the group.

From there, other groups may also be matched to that group but with a little more slop allowed between groups. You’ll see that a lot in Double Data Rate (DDR) memory. Address busses and data busses will be broken into byte lanes that have eight individual traces with a clock or a strobe pair that sets the target length.

 Single-ended transmission lines using tight serpentine to sync up a LiDAR sensor

Figure 1. Image Credit: Author - Single ended transmission lines using tight serpentine to sync up a LiDAR sensor

Differential Pairs - The Basis For Lowering Noise

Let’s unpack those groups. The most common scenario is a group of two nets we call a differential pair. A bit of electronic magic goes on when two lines are routed together vs. a single line. A single line carrying a stream of ones and zeros, actually just jumping between having a voltage present and not having a voltage will encounter other traces and shapes along its path. Those traces all want to share their noise conditions.

More exposure over longer lengths of trace lead to more crosstalk. Higher voltages extend the reach of the coupling effect. By the time the trace reaches its destination the journey may have added or subtracted enough stray voltage that the receiving end may not be able to distinguish a high state from a low state. The noise outweighed the signal and the receiver had to say, “What?” Then the sender sends the message again.

It’s acceptable for that to happen occasionally. There are usually a few clock cycles to spare. If it happens too often, the whole system breaks down. Every dropped packet of data increases the bit-error-rate (BER) and the system can only tolerate so many faults. Video can stutter, a call is dropped, the program crashes, the “Blue Screen of Death” ensues. Long high speed connections are the most susceptible to failure due to line losses and noise.

Enter differential pairs: They have much more immunity to the world around them because of the redundancy. Equal but opposite signals travel along the two paths and the receiver can compare the two signals and filter out the common noise. What’s left is a better representation of the original bit stream. Two is better than one when it comes to faster and longer communication across the board.

Differential pairs routed on a 12-Layer PCB

Figure 2. Image Credit: Author - Differential pairs routed on a 12-Layer PCB

Note in Figure 2 that the primary component layer is colored in cyan with magenta and orange on the inner routing layers. The red traces are single-ended and routed on the secondary component side. The gaps between the differential traces are equal to three times the line width. The FPGA (1) on the right side is fanned out with the diff-pairs gathered towards each other. Some pin-pairs are horizontal, some vertical, and others are diagonal in their orientation between the positive and negative terminals. The ground vias (green) tend to lean in towards the pairs.

Over on the QFP side, the signal vias are closely spaced and the ground vias are placed near the transitions. Ideally, all of the foursomes of signal and ground vias would be identical. The threesome on the lower-left-hand corner is a compromise. Halfway up that side, there are two pairs sharing three ground vias; another compromise.

When there is symmetry, the ground vias should be close to the signal pins. When they are asymmetric, it’s better to space the ground vias out a little. The sheer amount of horizontal routing drove the decision to place the ground vias in parallel with the signal vias. It was during the actual routing and tuning when the compromises became necessary.

Differential pairs perform at their best if their lengths are closely matched. We use what I call “speed-bumps” where one of the two traces makes a little jog to compensate for any length mismatch. In most systems, all that matters is the overall length and the phase-matching speed bumps can go anywhere along the lines.

In some cases, a turn in the two lines will get the waveforms out of sync enough to matter. At this point, we introduce a speed-bump to phase tune the pair at every corner. This is known as dynamic phase matching. A tight S-turn might be a wash but we’re aiming to keep the two signals running neck-and-neck for the entire flight. In this way, any transient voltage spike that washes over the layout will hit the two traces at the exact same time allowing the receiver to do its cancellation trick.

Imagine the interface of a camera when, all of a sudden, there’s a flash going off. The camera modules are usually located at a distance from the centrally located processor while they’re pretty close to the flash unit. The power for the flash unit does not have to be right next to the signal to add an instantaneous jolt of noise. Those signals are a prime candidate for differential routing. The standard MIPI interface takes this into account.

If a high-speed interface does not use differential signaling, then it is likely to have a maximum length that is on the shorter side. As an example, a type of flash memory that uses eMMC architecture comes to mind. The impedance for single-ended connections in a DDR memory bus is usually between 40 ohms and 50 ohms.

Graduate School Zone

A printed circuit board acts as a low-pass filter in the same way that a long coax would also attenuate high-frequency components of a signal. I use an LPF circuit on my bass rig to cut down the scratchy noise from the strings. That’s a good thing. When we’re talking about high-speed digital switching, the scratchy stuff is the part that matters. Turning down the treble is like slowing down the rise times which increases the bit error rate. The openings in the eye diagram get smaller. Low-loss materials give the signal more breathing room.

 A phenomenon called “skin effect” pulls the highest frequency part of the signal out to the perimeter of the traces. That makes the trace look narrower, more resistive as far as the pulses of data are concerned. Wider traces help but then you’re using more space in the X and Z dimensions in order to maintain impedance requirements.

An old trick from the analog world is to pre-distort the signal. Have you ever been tailgating and tried to listen to your car stereo from behind the car with the trunk open? It will be muffled and not beautiful. You can go in and set the tone control to where it’s like an ice-pick to your eardrums. Close the door and go back to the trunk and it may not sound perfect but it will be clearer to the point of being almost beautiful again.

That’s what predistortion can do at the driver pin side of the transmission line. There are feedback loops that are part of the firmware that kick in when too many bits fail to cross the divide between the send and receive ends of the signal. This kind of intelligent communication has to be part of any high-speed bit-stream. The additional pre-emphasis will consume more power so the better we can route those traces, the more efficient the system will be. Keep those eye diagrams open!

Becoming an expert at high speed and high-frequency signaling takes more than this chapter can offer. Therefore, I’d like to recommend the data sheets and application notes of long-established electronics firms such as Texas Instruments. More than mere data sheets, consider them as papers on topics of interest to the PCB designer.

They may be application notes for a specific processor but the guidelines are universal. They are written in plain enough language to understand the concepts. Their explanation of ground loops maybe twenty years old but the behavior is the same as it ever was. I know some folks discredit ap-notes and datasheets. While nothing is perfect, they’re far from useless.

“Every edge transition that is sent from the microcomputer to another chip is a current pulse. The current pulse goes to the receiving device, exits through that device’s ground pin, then returns via the ground traces, to the ground pin of the microcomputer (see Figure 3). The pulse does not exit the ground lead of the receiving device and return to the battery but travels in a loop to where it originates. Loops exist everywhere. Any noise voltage and its associated current travel the path(s) of lowest impedance back to the place where it was generated.”

Figure 3. Image Credit: TI - A diagram of the return paths on a typical PCB

The crystal loop is one to watch out for. I like to sever the direct connection of M-J from the rest of the ground plane. There is usually a ground pin or two near the XO pins that can be used to tie those caps back to ground. If not, then a moat around the crystal serves the same purpose.

There’s a symmetry in reducing noise emissions and increasing noise immunity. It’s a double benefit, or a double-edged sword if not handled correctly. Digital links become more like analog as the data rates climb. Serialized data lines will benefit from the same noise suppression techniques used in the analog world.

(1) An FPGA or Field Programmable Gate Array is a type of chip that can have logic assigned to the pins after the device leaves the foundry. Compare this to an ASIC or Application Specific Integrated Circuit where everything is hardwired. The FPGA is usually larger than an equivalent ASIC and is used in development. An ASIC is often a follow-on chip for production but FPGAs can be used at scale when development cost and time are at a premium.

Related Documents:

  • PCB Guidelines for Reduced EMI - Texas Instruments
  • High-Speed Board Layout Guidelines  - Altera (Intel)
  • High Speed Constraint Values and PCB Layout Methods - Charles Pfeil
  • IPC feature-article High-speed-PCB-design
  • IPC-4103B Specification for Base Materials for High Speed/ High Frequency Applications

Next - Section 7: Understanding and Prioritizing Buses


About the Author

John Burkhert

John Burkhert Jr is a career PCB Designer experienced in Military, Telecom, Consumer Hardware and lately, the Automotive industry. Originally, an RF specialist -- compelled to flip the bit now and then to fill the need for high-speed digital design. John enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. You can find John on LinkedIn.

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Section 5 – PCB Design: Fan Out Studies

Learn about fanout, miniaturization, and power planes

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Section 7 – PCB Design: Understanding/Prioritizing Busses
Section 7 – PCB Design: Understanding/Prioritizing Busses

Learn about busses and common bus types found on PCBs