Section 7 – PCB Design: Understanding/Prioritizing Busses

This is the seventh section in the back-to-school series for PCB Designers and those who may want to know more about it. 


Understanding and Prioritizing Busses

Memory, (see Section 8)  PCIe, SATA, USB.3, and Ethernet interfaces are likely the most sensitive to the layout. (1) Organize the fan-out vias so that the traces flow without crossing one another. If there must be twisted connections, try to minimize them during placement and even going back so far as schematic capture.

It may be possible to use pin swaps on an FPGA device to clean up the routing lanes. Busses should be given extra care starting with ideal component placement. Always consider the fan-out stage and any fine tuning that comes after routing during the pin re-assignment.

A rule-of-thumb on spacing is to use three times the thickness of the dielectric as a trace-to-trace air-gap. I’ve also seen it expressed in terms of line width times three but it’s the z-stack number that matters in most cases. The relationship between coupling and spacing is nonlinear. Cutting the space by half will square the amount of coupling so a little goes a long way whether adding or subtracting space.

Nested serpentine will use fewer corners than folding each trace into an accordion

Figure 1. Image Credit: Author - Nested serpentine will use fewer corners than folding each trace into an accordion.

More extreme isolation comes from putting a guard band around the bus or even between pairs within the bus. A guard band is a trace in the ground net that is staked to any relevant reference planes with a picket fence of vias. The idea is to create a “full metal jacket” of ground around the signals. The ideal spacing of the vias is a function of the rise time of the signals and the isolation requirements.

What we have in Figure 2 (see below) is an inner layer used to route four MIPI busses that are used as interfaces for camera modules. Each bus consists of four data pairs and one clock pair. The clocks are highlighted in yellow. Each pair in the bus is tightly matched within the pair so that the complementary P/N lines are the same length. That is the basis of differential routing.

Once that is achieved, the meanders are added so that the four data pairs are in sync with the clock pair. Then the four camera modules are grouped into left and right groups for the final length alignment. Each trace is a member of three cascading match-groups. Start with the lowest tolerance and work your way out to where there is the most latitude in terms of length matching.

Differential pairs routed on an inner layer of a circuit board

Figure 2. Image Credit: Author - Differential pairs routed on an inner layer.

In terms of the full metal jacket, it is lost towards the bottom-right corner of Figure 2 because I had to avoid routing under a big inductor. When it comes to magnetics, the sheets of copper planes do not contain the EMI field. Doing without the guard band between members of the same bus is preferable to routing below an inductor or transformer.

You might notice four single-ended lines that are also tinted to yellow. They are also clocks that are used for different purposes. Again, isolating them was done on a best-effort basis. Compromises had to be considered as they routed down past the power section where a stray via can cause noise problems. Doing real-world PCB design often involves managing risks in the least harmful way. As always, this job was a four-dimensional puzzle involving space and time.

Lower speed interfaces like I2C, I2S and JTAG can be given the less desirable real estate. That means that they can tolerate having a ground plane above and a power plane below the routing layer. It is best if the power plane is the same one that provides the voltage that drives the bus. It’s better not to hop over different power planes even with the low-speed connections.

In cases where the board does not have any high speed interfaces, the lower tier becomes the top tier. A motherboard may deprioritize the I2C where the daughtercard treats it like the main event. In that context, it is the most important set of connections. There will always be a hierarchy and there will usually be a layer of the board that is best suited for the routing. Adjust your effort accordingly.

Common Bus Types Found on PCBs

  1. PCIe - Peripheral Component Interconnect Express: This protocol comes in numerous types with anything from one to sixteen groups of TX/RX pairs. Data rates will depend on what is being connected. The phase matching between the P and N traces are insane.
    PCIe interface alignment
    Figure 3, Image Credit : Intel - PCIe is one of the few interfaces that have some latitude in the connectivity. If mirroring or rotating a component doesn’t solve the problem then polarity inversion and lane reversal are valid options.
  2. MIPI - Mobile Industry Processor Interface: Honestly, the only place I’ve seen this interface is between the SoC and the camera modules. Hololens AR and Pixel phones are the main culprits. Again, length-matching puts you on a grid of microns to clear the design rule violations.
  3. USB 3.0 - Universal Serial Bus gen 3 introduced “super-speed” to the design vocabulary. It’s a popular connection to the outside world but may also be implemented within the confines of a board.
  4. Ethernet - It’s been around for a long time and has gone through several improvements. MII stands for Media Independent Interface. Gigabit Ethernet uses GMII and more recently, Reduced Gigabit Media Independent Interface. They didn’t reduce the speed, just the number of wires for the same or greater bandwidth. Once the data becomes serialized, it also becomes differential. Ethernet goes from “not so bad” to “pretty bad” when it comes to dialing in the trace length.
  5. SATA - Serial Advanced Technology Attachment: That already spells trouble, doesn’t it? In the glory-days or parallel attachment, the processor talked to the hard drive with a 40-pin connector. Condensing that stream to a 15 pin connector and continually raising the speed limit makes this an interesting connection. Raising the bar further we have SATAe to put the data on the express train. See number 1 for what that can mean. SATAe goes into PCIe territory.
  6. HDMI - High Definition Multimedia Interface: The jump from VHS tapes to DVD disks was a quantum leap in data streaming. We cut the cord at Google when they put me on the Chromecast version 1. The drama was whether we could keep the routing on the top through a slot in the RF shield or bury the trace and suffer the consequences of using vias to tunnel under. EMI concerns won out and we buried the traces.
  7. SDIO - Secure Digital Input Output: This was the way Qualcomm talked to the outside world from the Snapdragon family of devices. It’s only four wires divided into TX and RX pairs but we were really picky about the routing with 25 micron maximum deviation between the positive and negative sides of the pairs.
  8. LVDS - Low Voltage Differential Signalling: A generic term with multiple uses, the low voltage indicates that the dielectric material for the PCB should be a low-loss/high-speed variant. If not, then it’s best to keep the lines relatively short. It’s a safe statement to make about any of the interfaces listed above.

There are a number of less critical interfaces where the penalty for each via is less severe. When you see functions like low-resolution video, high definition audio, the above-mentioned I2C or SPI, CANBUS, UART, or GPIO, the signal integrity is less of a concern but if any of those crop up as the board's main features, go ahead and treat them with care.

Graduate School Zone

Just as there is a best layer, there is likely to be a sketchy layer where routing is challenged by numerous split planes on one of the reference layers. Perhaps, the via-stubs on that layer present a problem for high speed routing. That layer can still be useful for escaping difficult sections. Routing short segments, just enough to find daylight on a better layer, will leave clusters of local traces with space between the clusters.

The layer may also be designated for power planes or as a last resort for emergencies. Define emergencies as the 11th-hour addition of a net that runs coast to coast. Putting the first revision to bed with one layer where the routing is sparse sets you up for a successful rev two. Room for improvement is always a good thing.

(1) Generally speaking, each bus will have its own set of constraints. Some are tighter than others. When the length matching tolerances are small, it’s a good sign that the bus is also susceptible to interference.

Related Documents

  • IPC-D-317 Design Guidelines for Electronic Packaging Utilizing High-speed Techniques

Next - Section 8: Memory Routing

About the Author

John Burkhert

John Burkhert Jr is a career PCB Designer experienced in Military, Telecom, Consumer Hardware and lately, the Automotive industry. Originally, an RF specialist -- compelled to flip the bit now and then to fill the need for high-speed digital design. John enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. You can find John on LinkedIn.

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Section 6 – PCB Design: Digital Routing

Learn more about digital routing and differential pair routing

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Section 8 – PCB Design: Memory Routing
Section 8 – PCB Design: Memory Routing

Learn about memory routing and DDR DRAM