Phase-locked loops are negative feedback-based electronic systems that adjust the output signal to match the frequency and phase of a reference signal.
Software PLL improves flexibility, as multiple PLLs can be incorporated and implemented.
Phase-locked loop-based clock generation is popular in data communication and radar applications, as it generates highly stable, low noise-affected, high-frequency clocks up to tens of gigahertz.
In wireless communication, phase-locked loops (PLL) are imperative blocks that enable clock recovery, frequency modulation, and demodulation. PLLs are extensively used in wireless base stations, CATV systems, wireless handsets, etc. We will cover some fundamental concepts of phase-locked loops and explore their applications in this article.
Phase-Locked Loops (PLL)
Phase-locked loops are negative feedback-based electronic systems that adjust the output signal to match the frequency and phase of a reference signal. The matching of frequency and phase of the signal with the reference is generally referred to as locking in PLL. When locked, the reference and the generated signal have no phase difference and they do not share the same frequency. In certain cases, there can be a constant phase difference between the two signals in a locked condition.
Internal Architecture of Phase-Locked Loops
The components that make the internal architecture of the phase-locked loop are:
Phase detector - The phase frequency detector is used for comparing the input reference signal with oscillator signal phases. This generates an error signal depending on the phase difference.
Loop filter - The output of the phase detector consists of high-frequency components. The loop filter, basically a low-pass filter, eliminates disturbances and high-frequency components and generates an error voltage from the error signal.
Voltage-controlled oscillator - Increases or decreases output frequency until it matches the input frequency. There can be zero phase difference or constant phase difference between the reference signal and the oscillator output signal.
In certain PLL, there can be a frequency divider in the feedback loop, which helps generate output signals with frequency signals to the multiplies of the reference signal.
Operation Stages of PLL
There are three operation stages for a phase-locked loop.
Implementation of PLL
PLL can be implemented in the following ways:
1. Analog PLL - Uses analog components such as an analog phase detector, loop filter, and voltage-controlled oscillator in a negative feedback loop. Numerous analog PLLs are available as off-the-shelf components.
2. Digital or hybrid PLL - Uses analog and digital components. Digital phase detectors and digital filters are most often used along with analog-controlled oscillators. Digital PLLs are smaller than analog PLLs.
3. All digital PLL - All the PLL elements are digital. The phase detector loop filter and voltage-controlled oscillator in all digital PLL are digital and completely customizable.
Software phase-locked loops are available, enabling PLL software implementation. Software PLL improves flexibility, as multiple PLLs can be incorporated and implemented. Usually, software PLLs are used for data or clock recovery.
Phase-Locked Loop Applications
There are numerous applications of PLL in wireless communication systems. They are used for frequency by synthesis, clock generation, phase modulation-demodulation, frequency modulation-demodulation, etc. In communication systems, especially satellite communication and wireless communication, where accurate and stable frequency reference is required, PLLs are widely used. Let’s look at the clock generation application of PLL in wireless communication systems.
In wireless communication, clock signals establish synchronization between the transmission and reception of signals. In wireless communication applications, phase-locked loops are used to generate clock signals with the highest degree of stability and accuracy. The high data rates in high-speed communication demand high-frequency system clocks with signal purity, stability, and frequency resolution.
Phase-locked loop-based clock generation is popular in data communication and radar application, as it generates highly stable, low noise-affected, high-frequency clocks up to tens of gigahertz. Cadence AWR Design platform can help you with circuit simulation of RF components including PLL. Leading electronics providers rely on Cadence products to optimize power, space, and energy needs for a wide variety of market applications. If you’re looking to learn more about our innovative solutions, talk to our team of experts or subscribe to our YouTube channel.