PCB Fanout For 0.4MM PITCH BGA Packages
Miniaturization continues to drive major changes in printed circuit board design. PCB design is one of those occupations that started off with big geometry that got smaller as the industry grew. This competitiveness is largely a function of the chip vendors aiming to one-up their rivals with higher density silicon in the data centers and beyond. That’s a win for marketing and a challenge to the PCB industry including those of us who design the fabric that ties it all together; the printed circuit board.
In this article, let’s discuss the following:
- Why so small?
- Stacked vs. staggered vias
- Fanout study: 133 pin WiFi/BT/FM combo device
There is a four-way cage-match going on with the chip house, the fab house and the assembly house with you in the other corner. You’re not alone. Your house includes electrical engineering, product design, SI/PI, Procurement and quite likely, a team of other engineers and subject matter experts (SMEs).
Project Management Includes People Management
Any chip on the board is likely to have its vendor requirements plus an internal SME within your group to tailor that data to its intended purpose. When it’s an in-house chip design, the whole company, or a work group within, is involved.
Figure 1. An HDI stack-up showing 9 of 12 layers. Image Credit: Author
Sometimes, the leadership will ask us how many layers and lamination cycles would do justice for the component. The answer will boil down to a range of possibilities from conservative to speculative. As always, the end-user has to be first priority.
They’re not in the room so you’re their advocate. Meanwhile, there is usually someone in the room who has no problem with adding risk to your best laid plans. Everyone is under pressure of some kind, just not the same kind. There’s bound to be conflict among the stakeholders.
Stacked vs. staggered vias
Figure 2. Staggering the vias, (right) is more disruptive to routing while stacking them saves space and is less convoluted. Image Credit: Author
Do we save money with staggered micro-vias or do we favor signal integrity with stacked micro-vias? Keeping everything moving in the same direction and finishing on time is part of our contribution to the program.
We walk a fine line to generate a stack-up and a trace geometry that works for everything. High density creates its own drama as intentional crowding adds uncertainty to new product development. Coexistence is a key metric so SI/PI is magnified.
Figure 3. The WLSCP version of this device includes a route free area (shaded). It could be for flatness or because RF elements are printed on the substrate in that area. Image Credit: Broadcom
Why 0.4 mm Geometry Is Different
The 0.4mm node is where BGA devices turn the corner. There is no routing between pins, only under them after transitioning to inner layers. The outer ring of pins creates an event horizon where nothing gets in or out on the surface. If you use layer 2 for routing the next row, then the one after that has to drill down to layer 3. We simply can’t route between the pins or the resulting vias at this density. It’s all in 3D with stacked vias or UHDI technology as the pin-count rises.
What If 0.4MM Pitch Is Still Too Big?
Of course, this technique will apply at the 0.35mm node as well. The pain-point becomes the diameter of the micro-via along with the resulting pad size. With this extra fine pitch BGA technology, we’re looking at soldermask defined lands. The metal layer grows a bit which allows the via to float within the pad without changing the definition of the solder joint. Coordinated micro-adjustments of the via locations within the pad may even open up an occasional routing channel. You learn to take what the footprint is giving you.
The “Ultra Fine Pitch” package scales it down to 0.3mm. To go below that, it’s chip-on-board (COB) where 0.2 mm pitch flipchips are the norm. They would normally go into a package with an interposer to spread out the signals. Chip companies can benefit from this technology for prototypes while waiting on the packaged silicon for mainstream production.
Figure 4. The so-called FCFBGA 133-pin package. I would avoid using any of the open areas where the balls have been depopulated. Image Credit: Author
This footprint, (see Figure 4) is giving us a lot. There are 12 rows and columns with 10 depopulated balls. On top of that, there are 28 ground pins (highlighted in green) and just as many no-connect pins in blue. So, 144 minus 68 pins that are missing, not connected or grounded and we’re down to 76 pins between voltage and signals.
That tracks well with the wafer level chip scale packaging (WLCSP) 89-pin package that Qualcomm used for these same three functions. Broadcom also has a reduced pin-count version where the blue pins are depopulated along with a larger form-factor. The WLSCP I could have showcased is a very tidy little GPS chip for this study, but something quirky has more lessons to share. Let’s dive into the fanout study.
Navigating the PDN in Dense BGA Layouts
The Power Domain Network is diverse. I can already picture nested power shapes around the device. Power is provided around the outside to the capacitors and then inward to the BGA voltage pins. Radio boards require a delicate touch on the PDN so whatever I do, there will be scrutiny. It will eventually be done with shapes but start with traces to stitch everything together.
Figure 5. The power tree has a few branches for this WiFi/Bluetooth/FM combo chip. Image Credit: Author
That big inductor in the upper right corner is as good as any to start. There always seems to be an external oscillator. This one is placed on the other side of the board and will require fully isolated connections. It’s almost like the XO pins are mapped to the edge of the package for no good reason. In a perfect world, the crystal would fit inside the shield.
It’s one of the things to consider during fanout. The placement is shifting around a little as it progresses. Using buried core vias is a good economic choice but creates a bottleneck in the via procession through the board from top to bottom. Getting away from the high density area on layers to avoid the core via under the BGA is going to allow more power and ground vias.
Figure 6. A sample of the pin descriptions which were written once and applied to three different packages for this table. Image Credit: Broadcom
Practical Approaches to Fine Line PCB Routing
In terms of the stack-up, layers could be arranged so that you have Ground, Signal, Signal, Ground configuration. The goal then becomes avoiding crosstalk on the paired signal layers. Routing orthogonally or at least between the traces of the adjacent layer is recommended. Thicker dielectrics between the signal layers relative to the ground pour is another way to inhibit crosstalk.
Sometimes, cross-talk is the point. In the case of differential pairs, routing the two traces on top of one another is just as valid as routing them side-by-side. Broadside coupling can be used in the fanout zone and then transition to edge coupled differential pairs further afield.
This might be preferable to necking down the diff-pair through the u-BGA zone. I’ve done entire boards full of 2.5 GB/s diff-pairs using only broadside coupling. It works as long as layer to layer misregistration is minimized.
Figure 7, Outer layer routing plus the supporting ground plane; making as many connections as practical. Image Credit: Author
Last Chance For Easy Placement Revisions
Doing the fanout dovetails with finalizing the placement. Up to this point, the components are fluid. What the fanout doesn’t include is the routing between devices. The circuit blocks can still be nudged around. Pin swapping is still on the table. A few new components are not yet a burden.
Figure 8. Layers 3 and 4. The trace/space design rules moved from 75 to 60 microns in to facilitate the fanout. The u-via padstacks shrank from 0.25mm to 0.22mm to create 180 gaps between vias. Image credit: Author
The layout is elastic for the moment. That changes once the inter-symbol connections materialize. The fanout forces us to consider the end game right from the start. A game of chess usually starts with a pawn move. Routing a tiny checkerboard filled with vertical connections is my definition of playing 4-D chess.