PCB Fanout For 0.5MM PITCH BGA Packages

The first printed circuit board packages that required High Density Interconnect (HDI) technology was the ball grid array (BGA) that used 0.5mm pin-to-pin pitch. Even though it’s entry level for HDI, it’s still a leap ahead of plated though-hole via technology. What are the differences?

In this article, let’s discuss the following:

• HDI stack-up
• Blind vs. buried vias
• Fanout study: 64-pin NFC device

Figure 1. HDI stack-up with thin dielectric materials enabling micro-vias. Image Credit: Author

One of the key features of the stack-up (see Figure. 1) are the multiple layers that are accessed using micro-vias. They are enabled by using thin dielectrics. The aspect ratio of the micro-via can be 1:1 at most whereas more vendors prefer via geometry where the diameter is greater than the depth of the via. Using 1.6:1 would be the conservative micro-via aspect ratio.

The dielectric thickness, (or thinness) also plays into the impedance calculations. These thin cores and prepregs lead to very thin traces for the typical 50 ohm transmission line. For longer routes, it may be necessary to hollow out the board in terms of the layers surrounding the micro-strip traces. Routing on layer-5 may call for relieving the adjacent copper on layers 4 and 6 so as to expose layers 3 and 7 for the reference planes.

Sequential Lamination Equals Time and Money

The fabrication would start with an 8-layer board defined by the buried core via that spans from Layer 3 to Layer 10 on the finished boards. Sequential lamination would add Layers 2 and 11 then, finally the outer layers on a third cycle through the press.

There is a micro-via from Layer 3 to Layer 4 as well as Layers 9 to 10 that we get without a lamination cycle. Those vias are created on the original 3-10 stack-up prior to the second lamination. Again, the cost is the thin dielectric in order to laser the micro-vias.

What Is a Micro-BGA?

By definition micro-BGAs begin where we can no longer support plated through-hole vias. I consider that threshold to be when the ball-pitch gets below 0.65 mm center to center. The common node just below that is the 0.5 mm pitch, where HDI begins. If we want to design a footprint for a chip of that scale, we start with the ball diameter. The pad size can be equal to the ball or slightly less, say 80% of the ball diameter as a rule of thumb.

Figure 2. Packaging alternatives for standard and high density interconnect. Image Credit: NXP

The sample BGA shown in Figure 2 will allow a single line between the balls provided a 3-mil line width on outer layers. The two substrates use the same silicon and have the same number of pins on the same pitch. The options are a plated through-hole board stack-up for the QFN and an HDI stack-up for the BGA. The larger form-factor will be better for high-reliability boards while the small one is more competitive in the mobile consumer market where size is a strategic concern.

Micro-BGA Pad Design: Balancing Yield and Reliability

When it comes to 0.5 mm BGA packages, Non Solder Mask Defined (NSMD) pads are generally preferred. The pads will be on the smaller side and the mask will be expanded for registration tolerance. Meanwhile, solder mask defined pads will have the mask encroaching on the pads. That overlap lets the solder joint collapse over the mask during reflow. That process creates a little ridge in the solder joint. It's a stress-riser that could be a reliability concern.

Let’s walk through a typical scenario when designing with a micro-BGA. The fabrication people like a board with the most robust technology so that they can get a higher yield and provide you with a lower cost. The assembly people like nice flat pads with consistent thermal characteristics for repeatable, compliant solder joints. Get both by calling out a flat surface for the via-in-pad. High yields for fab and assembly is a good thing but they can be at odds with each other.

Using The Application Notes To Your Advantage

Look at the u-BGA as a series of concentric rings of pads. Using via-in-pad-plated-over (VIPPO) techniques while maintaining the smaller geometry will allow the traces on the second ring to route out between the outermost ring. The trade-off for saving layers of material is that you limit the number of fab shops that can manage the smaller vias and trace geometry. Nobody said this would be simple.

Figure 3. Typical pin descriptions for PN7642EV/C100K NFC/RFID Read/Write 13.56MHz 256KB 64-Pin VFBGA. Image Credit: NXP

Some chip vendors advocate using a ground pour on the top layer and using layer 2 for the first signal escape path. My view is that the outer ring is going to be routed away from the chip on the top layer. The notion is keeping pressure off of the inner layers until there is no other choice. Alternatively, the perimeter pins could fanout on layer 2 to facilitate tighter component placement. This will depend on how you allocate the most expensive real estate on the board.

The farther in towards the center, the deeper the vias have to go to find a path out of the array. You could make exceptions for ground vias that go to a plane. Power pins would ideally be routed just one layer below that. No surprise that SI and PI will both want the best layers for their respective circuits.

Fine Lines Can Reduce Layer Count

It's probably more cost effective if you can squeeze two traces between vias. 500 micron pitch can be divided up like this: 250 micron via pads with 50 micron trace and space. If the vendors in your area cannot support the u-via size then you lose one of the routing channels and have to pay for a more involved layer stack-up to fanout the design. This via geometry is also for 0.4 mm pitch devices. You may only get one lane of routing between the rows of pins - and you’re happy to have it!

Figure 4. Initial placement with the following highlights: Green = GND, Magenta = PWR Dark blue = No Connect. Image Credit: Author

Around the device starting at the bottom and going clockwise, we have the crystal below and the RF matching networks to the left. Control and power circuits are clustered around the top and right respectively. There are 15 ground pins (green) six of which are strategically placed around the RF section.

We’re blessed with eight no-connect pins (dark blue) including the unused SPI interface and also three AUX pins which would be reserved for test access. The magenta pins represent the main power source while there are two smaller power domains as well. The chip includes a DC/DC up converter for the ARM core and multiple LDOs for the wireless section; a little something for everyone.

Figure 5. (Layers 12 and 11 shown) Taking advantage of no-connect pins to fanout the I2C nets from the center of the chip. Note how the ground plane has smaller shape-to-via clearance within the area of the NFC device. Image Credit: Author

Start the fanout with the outside rings and preserve routing channels for the inner rings. If you have controlled impedance, that's another matter that should be addressed early. You're going to have to experiment a little but I would avoid routing across the chip. Fanout away from the center no matter which way the traces ultimately go or it will take too many layers. Placement efforts should support the chip with the least convoluted routing for economy and performance.

Figure 6. (Layers 10 and 9 shown) Micro-vias transition to core vias on their way through to the other side of the PCB, mainly for power and ground connections. Image Credit: Author.

The thing to remember is this: There are levers that you can pull but there is usually another lever that moves along with it. An example: Narrow trace and space geometry will force the vendor to use thinner copper which may not work for your power planes. We have to adapt, improvise and overcome.