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Noise Margins on Low-Voltage Processor Cores

Noise margin processor core

Noise margin and noise floor are terms most often seen in analog electronics and in measurement analysis. In the past, no one really worried about noise margin on power unless they were dealing with a power regulator that had very strong overshoot on its output. Larger processors with more IOs and lower core voltages have changed the design approach for digital systems, and the trend is only expected to continue.

If you are building a digital system, the noise on the power rails must sit within some margin on top of the processor core voltage. When simulating system power or analyzing measurements of system power, you will need to compare noise measurements with the noise margin values you should expect to adhere to in your system.

Common Processor Core Voltage Values and Noise Levels

Processor IOs and power both have thin noise margins when core voltages start to become quite low. Most processors have multiple rails that must receive power at different voltages to support different features in the processor. For example, it's quite common to see processors have multiple rails at standard voltages, such as:

  • Analog interface supply voltage

  • Slower IOs at higher voltages (3V3)

  • Faster IOs at lower voltages (1V8 or 1V2)

  • Clock (PLL) power inputs (3V3, 1V8, or 1V2)

This is often the case on large processors like FPGAs, CPUs, GPUs, and even ASICs with high IO counts.

Examples of noise margins one might expect to see on rail voltages are shown below. The semiconductor industry has not standardized these noise margin values, only the voltage levels are standardized. Treat these noise margin values as an approximation and then use these to calculate a PDN impedance target.

Rail Voltage

Ripple target

3V3 (digital)


3V3 (analog)








These noise margins dictate the acceptable voltage ripple that can be experienced on each rail. Noise margin sets a limit on the allowed PDN rail impedance based on the peak current and allowed voltage excursion in a rail. For each rail, we can calculate a rail impedance using the peak voltage excursion as follows:

ZT =( Vsupply x ripple%) /( 50% x Imax)

The voltage excursion here should typically be taken as some value smaller than the noise margin. Include a safety factor in the design: anything from 20% to 50% for core voltage variation is appropriate. This value can then be verified from the physical PCB layout using 3D electromagnetic simulations and models for the components.

The value discussed here should also be verified at the input pins of the supported processor or ASIC. PDN impedance measurements are not direct measurements due to the fact that they involve many components and difficulty in defining the physical path for a TDR pulse. Instead, PDN impedance values are verified using S-parameters or direct measurements of the output voltage ripple alongside input current. These measurements can also be compared with your voltage excursion and PDN rail impedance values for design verification.

Design Approach With Multiple Low Noise Rails

We sometimes communicate digital PDN design as something that only involves one rail that can be put into a single plane layer. Given the large number of rails and the diversity of their voltage levels, real digital systems with large processors and advanced ASICs use a more advanced approach to physically construct a PCB for these systems.

Noise margin processor core

Each block in this topology could have its own regulator to isolate certain processor features from noise on other rails.

Rails placed in the PCB can originate from one main regulator which is then further stepped down using VRMs. The role of a VRM on one rail is to isolate it from other rails and to tightly regulate a specific core voltage up to very high frequency. The bandwidth of the control loop in the VRM will determine the frequencies at which it can regulate, with typical values reaching into the hundreds of MHz before the chip’s PDN takes over. This would be applied across all rails that need to supply power for high-speed interfaces.

To ensure success in these designs, follow some simple tips for PDN system design:

  • Examine regulator control loops to ensure they support your system bandwidth

  • Examine noise rejection values on regulators

  • Consider running switching regulators at higher frequency to reduce noise and inductor sizes

  • Do not try to isolate to rails supplying different IOs groups connected to the same regulator, just use two regulators instead

  • Use a single ground for all rails rather than physically disconnected grounds as this will aid high speed routing

For a good example of this type of system and the design approach, take a look at our recent FPGA design project. This project uses a Xilinx FPGA with multiple rails and core voltages to provide power for many high-speed and low-speed IOs. Some of the interfaces included in the design are LVDS, DDR, CSI, SATA, and QSPI.

If you want to eliminate NFPs on select through-holes, make sure you have CAD tools that make it easy. Multi-disciplined design teams rely on the best set of PCB design features in Allegro PCB Designer from Cadence. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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