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Overview of Improved Inter-Integrated Circuit (I3C)


Legacy serial interfaces like I2C and SPI are well-known amongst designers, even new designers that are still learning how to design PCBs. These interfaces are not going away anytime soon due to the wealth of components that implement the I2C interface as a standard feature. But that still leaves room for improvement due to known challenges on I2C buses, even when only running at moderate speed.

The newest iteration of the legacy I2C standard is known as improved inter-integrated circuit (I3C) communication. This new MIPI standard is intended to retain some backward compatibility with legacy I2C capable devices, yet providing improvements on known problems in I2C buses. Among the improvements are new approaches to bus management and error handling, higher data rate allowance, and a dynamic addressing scheme.

How I3C Works

MIPI I3C is very similar to legacy I2C in that it uses a 2-wire interface to communicate with multiple peripherals on a single bus. The interface allows bidirectional half-duplex communication at higher data rates than are used in I2C. In the I3C standard, the primary goals in development were to reduce the number of pins required on the bus, enable lower power data transfer with open-drain signaling, and maintain compatibility with legacy devices.

The table below compares the main features of I2C and I3C.




Data Rate

Up to 33 Mbps

Up to 1 Mbps (Fast-mode Plus)

Power Efficiency

More power-efficient with in-band interrupt and lower operating voltages

Less power-efficient compared to I3C


More complex due to advanced features

Simpler in design and operation

Backward Compatibility

Backward compatible with I2C devices


Bus Management

Advanced with dynamic addressing and hot-joining capabilities

Basic, lacks dynamic addressing and hot-joining

Error Handling

Enhanced error detection and recovery mechanisms

Basic error handling

Communication Modes

Supports SDR and HDR modes, along with traditional I2C-like modes

Standard I2C communication mode

The backward compatibility and directionality essentially allow components on an I3C bus to have the same basic topology as on an I2C bus. The additional features in the I3C bus allow multiple I2C devices and a secondary I3C master to be present on the bus alongside standard I3C peripherals. Normally, I2C would allow more than one controller on the bus, but only as long as they were transmitting in their own time windows. I3C allows multi-master buses without the collision problems in I2C buses thanks to a built-in arbitration system.

The typical topology is shown below, where both I2C and I3C devices are connected to the bus. The bus could have multiple I2C or I3C target devices, and I3C secondary master components, as needed in the system.


On a PCB, the bus would still be laid out in the standard way due to the use of open-drain signaling:

  • Use large pull-up resistors to limit current into the open drain on drive pins

  • Use a capacitor to set the signal transition rate (rise time)

  • Typical rise times of ~100 ns are still acceptable for I3C based on the clock rate

Routing the traces in the standard way for an I2C bus completes the physical design for an I3C bus.

What is Dynamic Addressing?

The three most important features in I3C are dynamic addressing, hot joining, and collision avoidance with multi-master buses. The use of dynamic addressing intends to reduce the number of pins on the bus by eliminating the need for address pins. To use dynamic addressing:

  • The master sends an initial command to the devices to initiate DAA.

  • Devices without an assigned address respond with their 48-bit Provisional ID (PID), a unique identifier.

  • The master then assigns a dynamic address to each device based on the PID.

  • The peripheral stores the dynamic address in a register

Because addressing can be made dynamic, addresses for peripherals can be changed later. Static addressing on a peripheral can still be used, such as on a legacy I2C device connected to the I3C bus.


An I3C bus supports a process known as hot-joining (think hot-swapping), where new devices can be added to the bus while it's operating. For example, if you plug a module with an I3C device into a hot connector, and that connector exposes the I3C bus pins, the new I3C device can be added to the bus by the I3C master.

The newly connected I3C device needs to signal its presence to the I3C master. This is performed via a hot-join request, where the new device sends a signal indicating it intends to join the bus. Once the master acknowledges the new device, it can assign an address as required and then begin communication.

When you’re ready to design a product that uses I3C interfaces, make sure you use the best PCB design features in OrCAD from Cadence. If you’re ready to take even more control over net logic and board layout, you can graduate to Allegro PCB Designer for a more advanced toolset and additional simulation options for systems analysis. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.

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