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Target Impedance Values in PDN Design

Circuit board with power supply

Whoever designed the Jenga blocks deserve a spot in the hall of fame. What started with a neat arrangement of crisscrossing wooden blocks always ends up in adrenaline-charged excitement as the tower wobbled to the slightest of touch. For some reason, it was always my clumsy hands that brought it down, to the triumphant cries of others.

You won’t be playing Jenga in PCB design but as semiconductors are powered by decreasing voltage values, the margin of tolerance of voltage fluctuation becomes smaller. In a sense, it’s like a Jenga block stacked with impossible geometry as the slightest ripple may result in EMI issues.

What Are Target Impedance Values

The term target impedance is almost unheard of when electronics are operating in the domains of 5V. Back then, a variation of 200 mV is unlikely to cause any issues to any of the components on board. But as voltage requirements of semiconductors nosedives to the like of 1.8V or below, 200 mV is suddenly a tsunami on the voltage plane.

Target impedance becomes a critical value on the power delivery network to ensure that fluctuations are kept to an acceptable range. The target impedance value of a design is given by the equation:

ZT =( Vsupply x ripple%) /( 50% x Imax)

The formula represents a combination of voltage fluctuation and transient current. At its worse, this combination has the potential to affect the signal and power integrity of the circuit. The ‘ripple%’ points to the maximum voltage deviation where some of the components become dysfunctional.

Therefore, the job of a PCB designer is to keep the impedance of the power delivery network (PDN) below the target impedance value. Keeping the impedance of the PDN low isn’t about having larger power planes or placing more decoupling capacitors. Target impedance is a function of frequency, and this means ensuring that the value across the operating frequency is below the threshold. 

Dealing With Target Impedance Peaks

The trick to ensuring that the PDN design satisfies the target impedance is to have the value stay below the limit. However, this is easier said and done. A circuit typically contains hundreds of components with capacitive and inductive properties. Also, there is parasitic inductance on the pads, joints, and trace that may lead to an increase of the PDN impedance value.

To further complicate the matter, you may have to deal with target impedance peaks across a broad range of frequencies. At certain frequencies, the peak may breach the target impedance which will compromise the functionality of the circuit. Even if the peak stays below the limit, the circuit is not perfectly safe.

Digital oscilloscope measuring electronics

At lower voltage points, the slightest ripple may cause a significant impact.


When a transient voltage occurs at the resonant frequency of the peak, the amplitude of the resulting voltage swing may exceed the nominal voltage given by the target impedance equation. Of course, this is influenced by the q-factor of the circuit, which defines the damping effect of the resonance. The effect of resonance must be taken into account when determining the PDN impedance of the design.

Helpful Tips In Decreasing Target Impedance Values 

The key to lowering target impedance values is to reduce inductance and increase the capacitance of the PDN. Placements of decoupling capacitors matter, as it could alter the value of both parameters. The capacitors should be placed on the same layer of the chips supply pin to minimize inductance. 

Capacitors on a printed circuit board

Adding capacitors help lower PDN impedance

If you’ve identified resonance peaks that have breach the target impedance value, a quick fix is to add capacitors to decrease the resulting impedance. It’s also important to visualize how current flows in the PCB and to minimize current loops as they add on to parasitic inductance. 

There’s also a concern of over-optimizing the target impedance value for the PDN. An overtly-cautious approach often results in adding redundant components and extra development hours, which translate into unnecessary costs.

Determining the impedance value of the PDN involves tedious calculation. You’ll be better off with a handy PCB design software that aids you in the process. With OrCAD PCB Designer you’re guaranteed a layout and schematic tool that will provide anything you need throughout your design validation process. 

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.