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How to Start an FPGA PCB Layout

FPGA PCB layout

After a generation of embedded engineers was trained on platforms like Arduino and Raspberry Pi, FPGAs are now coming back in style among embedded systems engineers. Applications like IoT, 5G, embedded AI, and much more can greatly benefit from the customizable configuration capabilities in FPGAs. These powerful components bring with them a set of design challenges that can be difficult to overcome if not

If you choose to include an FPGA in your PCB layout, there are some floorplanning steps required to ensure successful design and manufacturing. There is also a need to match the board construction to the configuration implemented in the FPGA. In this article, we’ll look at some strategies for floorplanning PCBs for FPGA-based systems. These design points cover signal integrity, power integrity, EMC, and manufacturability.

How to Floorplan With an FPGA

An FPGA is a reconfigurable processor that allows a variety of code to be implemented at the hardware level. The logical architecture used in an FPGA allows developers to implement totally custom logic, as well as standard digital interfaces. Many of today’s advanced computing and networking products are built around FPGAs manufactured at advanced processing nodes. Some examples include 100 GbE controllers, AI accelerators in data centers, and advanced computing products like edge node servers.

To help ensure your FPGA will be manufacturable and easy to route, make sure to follow a few important steps when starting your PCB layout.

Verify the FPGA Footprint and Fanout

Most FPGAs that are available on the market today are packaged as BGAs, so there will be some important points to check in the PCB footprint:

  • Check if NSMD vs. SMD pads are needed
  • Determine if dogbone fanout or via-in-pad is needed based on ball pitch
  • Determine ball clearance for traces in routing channels
  • Use the previous point to determine the appropriate layer thickness for impedance controlled channels

FPGA PCB layout

Via-in-pad is implemented in this BGA footprint.

These design points are intended to ensure manufacturability of the finished board. These points will affect routing if not considered, and no one wants to rip up a bunch of routing because they neglected to check clearances and trace widths before starting the PCB layout. The corresponding design task to the PCB footprint is to create the stackup, but this should be done based on the interfaces being instantiated in the FPGA.

Select IP, Then Plan the Stackup

A big part of designing with FPGAs is selecting vendor IP to implement in silicon. FPGA IP is provided by the component manufacturer to implement standard digital interfaces or application-specific processing that are not pre-packaged in the component. Selecting IP is the first step in customizing the available I/O space within an FPGA so that the component is more tailored to your application.

IP is normally selected to expand the available digital interfaces on an FPGA to a larger number, or to a less popular interface that might not be standard on the FPGA die. Because these are normally high-speed digital interfaces, it’s best to start with the impedance requirements so you can plan the PCB stackup.

An example stackup for a 6-layer PCB that could support a moderate size FPGA is shown below. In this stackup, we are

L1: Signal

High-speed routing channels


Make this layer thinner so that microstrips on L1 have smaller width

L2: Ground

Solid ground plane


Make this layer thinner to provide high plane capacitance

L3: Power

Solid power plane or dedicated to power rails


Central core layer (thicker)

L4: Signal

High-speed routing channels


Make this layer thinner to control impedance for signals on L4

L5: Ground

Solid ground plane


Make this layer thinner so that microstrips on L6 have smaller width

L6: Signal

High-speed routing channels

Note that the signal layer count will depend on the number of required routing channels, which would be determined in the usual way by examining the number of row/column pairs in the FPGA’s BGA footprint.

Plan Your Routing Channels

Once you’ve made sure the footprint will comply with DFM requirements, and you’ve determined the number of required layers to support your I/O banks and PWR/GND, it’s time to think about planning routing channels. Floorplanning around an FPGA has a lot more freedom because the device is reconfigurable, and routing channels will be determined partially by the pin assignments you provide in your vendor development tools.

FPGA PCB layout

Routing channels require optimal pin assignments that are oriented towards the destination component. The example above shows how routing channels into a connector are affected by pin assignments. [Source: Cadence Community]

From the above image, it’s easy to infer that improperly selected pin assignments will make routing much more difficult. In the event you find that your routing will be difficult due to suboptimal pin assignments, use the pin swapping tool to reorganize pins in the FPGA and redesign your routing channels.

If you’ve decided an FPGA PCB layout is the best path forward for your system, make sure you have the best design, layout, and routing utilities in Allegro PCB Designer from Cadence. Only Cadence offers the best PCB design and analysis software that includes industry-standard CAD tools, powerful routing features, and much more. Cadence also has FPGA system floor planning and development tools to help ensure FPGA design success.

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