Mixed-signal systems must balance elements that are critical in the digital domain as well as the analog domain. One important area of digital interface design in mixed-signal systems is clocking, which must be used to enforce timing between components and to read data from ADCs. Many mixed-signal systems operating in the low-to-moderate frequency range will use a reference oscillator, and there may be a need to synchronize multiple clocks across a system to accurately sample and synchronize the entire system.
ADC Clocking Requirements
Clocks for ADCs come in a few different forms:
- A clock can be a reference oscillator, usually a crystal oscillator
- The digital interface may include a clock, such as a source-synchronous interface like SPI or I2C
- The system processor could source a system clock signal for multiple components, including an ADC
- High-frequency ADCs may require a clock signal generated from a PLL
Clocking is needed to set the sample rate of the converter, as well as to synchronize multiple ADCs should they be present in a mixed-signal PCB. When sampling from multiple ADCs, or when using an ADC alongside other clocked components with a system clock, the ADC can be sampled synchronously or asynchronously. The clock signal also needs to have low jitter to ensure accurate signal sampling at the analog input.
Clock Jitter in ADCs
One very important aspect of ADC clocking is jitter on the clock signal. The clock signal will determine the sampling bandwidth of the ADC input interface for the analog signal. If the source oscillator has unstable power, or it receives noise from another source, it could have excessive jitter that reduces conversion accuracy in the ADC.
When the clock signal has more jitter, the sampling bandwidth spreads out and its gain decreases. The result is that the sampled signal will appear to have higher noise and lower SNR value than the real signal. This occurs because the input interface’s transfer function has spread over a larger bandwidth, which will include more of the signal chain’s noise within the measurement bandwidth.
The result is that the jitter will limit the maximum SNR value of the sampled signal in the ADC at a particular frequency, i.e., jitter forces the ADC to collect more noise. An example showing SNR vs. frequency curves for various jitter values in a real component (AD7668-1) is shown below.
Example showing how jitter affects SNR in a real ADC [AD7768-1, Source: Analog Devices]
When sampling very low-level signals, a successive set of filtering, amplification, and conditioning stages is needed to increase the signal’s noise-free dynamic range and extract the desired signal from noise. However, the reference oscillator also needs to be extremely stable for the reasons described above.
In synchronous sampling with multiple ADCs, all the ADCs are synchronized to a system clock, or to a source-synchronous clock on an input digital interface (usually SPI). The SYS_CLK net in the block diagram below does not need to be a system oscillator like a single crystal; it could be a reference signal from a processor or the SCK signal on one of the SPI interfaces.
ADC synchronous clocking example.
It is generally expected in designs that use a system clock that everything will be synchronous everywhere; this is the entire reason people used system clocks. This is one reason that source-synchronous protocols were created; they help to eliminate the difficulties in synchronizing fast clocks with fast data streams. However, systems with multiple ADCs can also operate asynchronously, where the ADCs use separate oscillators to set sampling rates and collect output data.
In asynchronous clocking, the ADCs have their own oscillators and they are not necessarily synchronized to the same clock signal or the same sampling rate. The ADCs shown in the example below have their own SPI interfaces; the CLK signals are the SCK signals in each interface in the example. However, they could generally be provided by separate reference oscillators or crystals.
ADC asynchronous clocking example.
This is useful when multiple ADCs need to sample at different rates, and this is where it is desirable to take advantage of a source-synchronous protocol to clock the ADC and extract the sampled data.
At Higher Speeds - Use JESD204 Compliant Parts
When higher-speed digital interfaces are being used with much faster ADCs with high Msps or Gsps sample rates, an alternative method may be needed to synchronize data from the system. In general, there are two techniques involved in these systems:
- Use a PLL with a reference oscillator to produce the required clock frequency
- Use a digital interface with an embedded clock that can be easily routed across multiple components
#1 is only useful in the case with a single ADC, or with asynchronous sampling of multiple ADCs. It is very difficult to use source-synchronous PLL clocking with multiple ADCs because skew at high frequencies will be unpredictable, leading to potential desynchronization of the ADCs. A PLL is designed to clean up jitter from a reference oscillator like a crystal, but out-of-band noise in the PLL noise floor can still decrease the SNR value of the sampled signal when operating in the GHz range.
An alternative to use a GHz PLL is to use ADCs with a JESD204 interface (newest revision: JESD204C). The JESD204C interface uses embedded clocking that synchronizes sampling and data output from the ADC. As long as the driver component layout can control jitter and the interface is routed with low enough skew, multiple ADCs can be clocked and synchronously sampled more accurately than with a single PLL routed in a source-synchronous clocking fashion.
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