Cadence PCB Best Practices
High Density Interconnect (HDI)
Issue link:
https://resources.pcb.cadence.com/i/1180282
Contents of this Issue
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Articles in this issue
Cover
Contents
Working with HDI
Microvias and Padstacks
Non Standard Drill Types
User-Definable Mask Layers
Plural Microvias
Blind and Buried Via Span Labels
Via List Enhancements
Same Net DRC Overview
Constraint Manager – Same Net Spacing Domain
Same Net Constraint Set
Same Net Spacing Modes
Same Net Spacing - DRC Markers
Etch Edit Support for Same Net Rules
Constraint Regions
Via-in-Pad Overview
Component Fanout
Via-in-Pad DRC Suite
Via in Pad DRC Mode Settings
Property Overrides
HDI Via Structures
Working Layer Model
Add Via Popup Interface
Ordered Via List
Stacked HDI Vias
Staggered HDI Vias
HDI Utilities
Line Fattening between Tangent Vias
Elimination of Unused Blind and Buried Vias in a Stack
Unused Blind and Buried Via Report
Dynamic Unused Pad Suppression
User Interface
Layer Restrictions
Other Restrictions
Dynamic Suppression
Exception Properties
Artwork Alignment
Router Interface
Drill to Metal DRC
Constraint Manager Integration
Dynamic Filleting
Shape-based Fill
Parameters
Fillet Algorithm
Reporting
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