Issue link: https://resources.pcb.cadence.com/i/1180282
High Density Interconnect Working with HDI October 2019 20 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. the constraint set via list for the layers upon which you want to route; however, this mode assumes that you have defined an "ordered via list" for CSets in Constraint Manager. The vias listed in the Edit Via List are available for adding when you route interactively For more information, see Setting Up Ordered Via Lists in Chapter 8 of the Routing the Design user guide in your documentation set. Stacked HDI Vias A via stack comprises two or more Same-Net vias that are directly connected at the same location, with adjacent vias in the stack each sharing one common layer. A Split Stack option available from a right-mouse popup menu allows one or more vias to be split from their via stack if required. When sliding a via (or stack of vias) outside the pin pad, a cline is added as necessary to avoid orphan vias, or those that become disconnected from the net. For more information, see Multiple Vias With Stacking Not Allowed in Chapter 8 of the Routing the Design user guide in your documentation set. Staggered HDI Vias A microvia on one layer connecting to a via on the second layer can be staggered, or offset such that the pad diameters are tangential or greater when vias are not allowed to be stacked. For more information, see Multiple Vias With Stacking Allowed in Chapter 8 of the Routing the Design user guide in your documentation set. HDI Utilities HDI design utilities automate interactive tasks, among them a line-fattening program that increases line width between tangent HDI vias, and a report and gloss application that detect and remove unused blind and buried vias in a stack. Line Fattening between Tangent Vias A post-route task associated with HDI design increases the line width between two tangent vias based on a user-defined, edge-to-edge clearance to remove the acute angle formation between the vias' junction.